Abstract: In the measurement of properties of a wafer substrate, such as Critical Dimension or overlay a sampling plan is produced defined for measuring a property of a substrate, wherein the sampling plan comprises a plurality of sub-sampling plans. The sampling plan may be constrained to a predetermined fixed number of measurement points and is used to control an inspection apparatus to perform a plurality of measurements of the property of a plurality of substrates using different sub-sampling plans for respective substrates, optionally, the results are stacked to at least partially recompose the measurement results according to the sample plan.

Abstract: In the measurement of properties of a wafer substrate, such as Critical Dimension or overlay a sampling plan is produced defined for measuring a property of a substrate, wherein the sampling plan comprises a plurality of sub-sampling plans. The sampling plan may be constrained to a predetermined fixed number of measurement points and is used to control an inspection apparatus to perform a plurality of measurements of the property of a plurality of substrates using different sub-sampling plans for respective substrates, optionally, the results are stacked to at least partially recompose the measurement results according to the sample plan.

Abstract: In the measurement of properties of a wafer substrate, such as Critical Dimension or overlay a sampling plan is produced defined for measuring a property of a substrate, wherein the sampling plan comprises a plurality of sub-sampling plans. The sampling plan may be constrained to a predetermined fixed number of measurement points and is used to control an inspection apparatus to perform a plurality of measurements of the property of a plurality of substrates using different sub-sampling plans for respective substrates, optionally, the results are stacked to at least partially recompose the measurement results according to the sample plan.

Abstract: In the measurement of properties of a wafer substrate, such as Critical Dimension or overlay a sampling plan is produced 2506 defined for measuring a property of a substrate, wherein the sampling plan comprises a plurality of sub-sampling plans. The sampling plan may be constrained to a predetermined fixed number of measurement points and is used 2508 to control an inspection apparatus to perform a plurality of measurements of the property of a plurality of substrates using different sub-sampling plans for respective substrates, optionally, the results are stacked 2510 to at least partially recompose the measurement results according to the sample plan.

Abstract: In the measurement of properties of a wafer substrate, such as Critical Dimension or overlay a sampling plan is produced 2506 defined for measuring a property of a substrate, wherein the sampling plan comprises a plurality of sub-sampling plans. The sampling plan may be constrained to a predetermined fixed number of measurement points and is used 2508 to control an inspection apparatus to perform a plurality of measurements of the property of a plurality of substrates using different sub-sampling plans for respective substrates, optionally, the results are stacked 2510 to at least partially recompose the measurement results according to the sample plan.

Abstract: In the measurement of properties of a wafer substrate, such as Critical Dimension or overlay a sampling plan is produced 2506 defined for measuring a property of a substrate, wherein the sampling plan comprises a plurality of sub-sampling plans. The sampling plan may be constrained to a predetermined fixed number of measurement points and is used 2508 to control an inspection apparatus to perform a plurality of measurements of the property of a plurality of substrates using different sub-sampling plans for respective substrates, optionally, the results are stacked 2510 to at least partially recompose the measurement results according to the sample plan.

Abstract: In the measurement of properties of a wafer substrate, such as Critical Dimension or overlay a sampling plan is produced 2506 defined for measuring a property of a substrate, wherein the sampling plan comprises a plurality of sub-sampling plans. The sampling plan may be constrained to a predetermined fixed number of measurement points and is used 2508 to control an inspection apparatus to perform a plurality of measurements of the property of a plurality of substrates using different sub-sampling plans for respective substrates, optionally, the results are stacked 2510 to at least partially recompose the measurement results according to the sample plan.

Abstract: In the measurement of properties of a wafer substrate, such as Critical Dimension or overlay a sampling plan is produced (2506) defined for measuring a property of a substrate, wherein the sampling plan comprises a plurality of sub-sampling plans. The sampling plan may be constrained to a predetermined fixed number of measurement points and is used (2508) to control an inspection apparatus to perform a plurality of measurements of the property of a plurality of substrates using different sub-sampling plans for respective substrates, optionally, the results are stacked (2510) to at least partially recompose the measurement results according to the sample plan.

Abstract: In the measurement of properties of a wafer substrate, such as Critical Dimension or overlay a sampling plan is produced (2506) defined for measuring a property of a substrate, wherein the sampling plan comprises a plurality of sub-sampling plans. The sampling plan may be constrained to a predetermined fixed number of measurement points and is used (2508) to control an inspection apparatus to perform a plurality of measurements of the property of a plurality of substrates using different sub-sampling plans for respective substrates, optionally, the results are stacked (2510) to at least partially recompose the measurement results according to the sample plan.

Abstract: A method of optimizing a die size in a method of manufacturing devices using a lithographic apparatus, wherein the lithographic apparatus is arranged to expose an image field of variable size in a single exposure step, the image field having a certain maximum size, the method comprising: receiving a desired area for the die; and calculating a target aspect ratio for the die, wherein the target aspect ratio is determined so as to maximize the number of good dies that can be imaged per hour using the lithographic apparatus. Desirably, calculating a target aspect ratio comprises finding a first target aspect ratio that maximizes a figure of merit MF, where MF is the ratio of the number of dies exposed in each image field divided by the number of exposures on each substrate.

Abstract: A method of optimizing a die size in a method of manufacturing devices using a lithographic apparatus, wherein the lithographic apparatus is arranged to expose an image field of variable size in a single exposure step, the image field having a certain maximum size, the method comprising: receiving a desired area for the die; and calculating a target aspect ratio for the die, wherein the target aspect ratio is determined so as to maximize the number of good dies that can be imaged per hour using the lithographic apparatus. Desirably, calculating a target aspect ratio comprises finding a first target aspect ratio that maximizes a figure of merit MF, where MF is the ratio of the number of dies exposed in each image field divided by the number of exposures on each substrate.

Abstract: A lithographic apparatus configured to transfer a pattern from a patterning device onto a substrate includes an integrated post-exposure bake device, the post-exposure bake device configured to subject the substrate to a predefined temperature cycle. A post-exposure bake step of the substrate (a temperature cycle) is executed within a predetermined time period after the transfer of the pattern. The lithographic apparatus may be combined with a processing system having one or more processing modules. More efficient use may be made of the combination, allowing flexibility for a device manufacturing method.

Abstract: A rework station and a metrology device(s) are incorporated into a lithographic processing cell so that a faulty substrate can be reworked directly and reprocessed without, for example, an overhead involved in changing masks, etc.

Abstract: A rework station and a metrology device(s) are incorporated into a lithographic processing cell so that a faulty substrate can be reworked directly and reprocessed without, for example, an overhead involved in changing masks, etc.

Abstract: A rework station and a metrology device(s) are incorporated into a lithographic processing cell so that a faulty substrate can be reworked directly and reprocessed without, for example, an overhead involved in changing masks, etc.

Abstract: A lithographic apparatus configured to transfer a pattern from a patterning device onto a substrate includes an integrated post-exposure bake device, the post-exposure bake device configured to subject the substrate to a predefined temperature cycle. A post-exposure bake step of the substrate (a temperature cycle) is executed within a predetermined time period after the transfer of the pattern. The lithographic apparatus may be combined with a processing system having one or more processing modules. More efficient use may be made of the combination, allowing flexibility for a device manufacturing method.

Abstract: A method of device inspection, the method comprising providing an asymmetric marker on a device to be inspected, the form of asymmetry of the marker being dependent upon the parameter to be inspected, directing light at the marker, obtaining a first measurement of the position of the marker via detection of diffracted light of a particular wavelength or diffraction angle, obtaining a second measurement of the position of the marker via detection of diffracted light of a different wavelength or diffraction angle, and comparing the first and second measured positions to determine a shift indicative of the degree of asymmetry of the marker.

Abstract: A method of device inspection, the method comprising providing an asymmetric marker on a device to be inspected, the form of asymmetry of the marker being dependent upon the parameter to be inspected, directing light at the marker, obtaining a first measurement of the position of the marker via detection of diffracted light of a particular wavelength or diffraction angle, obtaining a second measurement of the position of the marker via detection of diffracted light of a different wavelength or diffraction angle, and comparing the first and second measured positions to determine a shift indicative of the degree of asymmetry of the marker.