Abstract: A data processing apparatus and method are provided for managing polling loops. The data processing apparatus comprises a main processing unit and a subsidiary processing unit operable to perform a task on behalf of the main processing unit. The subsidiary processing unit is operable to set a completion field when the task has been completed and the main processing unit is operable to poll the completion field in order to determine whether the task has been completed. If on polling the completion field a threshold number of times the main processing unit determines that the task has not been completed, the main processing unit is operable to enter a power saving mode. The subsidiary processing unit is operable, when the task has been completed, to cause a notification to be issued on a path interconnecting the main processing unit and the subsidiary processing unit. The main processing unit is arranged, upon receipt of the notification to exit the power saving mode.

Abstract: A data processor 2 has privilege levels associated with it including a user level and a privileged level. The processor 2 also has multiple stack memories which can be used including one or more process stacks, a main stack and a deep stack. The stack memory to be used is de-coupled from the privilege level. An activation level state variable tracking the number of pending exceptions is held by the processor and used to modify which stack memory stores pending state values when an exception occurs. If the system is at a base level of activation, corresponding to currently no pending exceptions, then when an exception occurs the current state data is saved on the process stack with the main stack being available for the exception handling code. Particular exceptions can be flagged as requiring use of a deep stack rather than either the process stack or the main stack.

Abstract: A system is described having a JTAG diagnostic unit and a serial wire diagnostic unit. A watcher unit is connected to a data connection shared between the diagnostic units. Special patterns detected upon the shared data connection serve to switch between diagnostic modes with respective ones of the diagnostic units becoming active.

Abstract: This disclosure describes a processor system that allows non-real time code to execute normally, while permitting a real time interrupt in hardware or software to execute with minimal added latency.

Abstract: This invention relates to multi-core, multi-processing, factory multi-core and DSP multi-core. The nature of the invention is related to more optimal uses of a multi-core system to maximize utilization of the processor cores and minimize power use. The novel and inventive steps are focused on use of interrupts and prioritized interrupts, along with optional in-built methods, to allow systems to run more efficiently and with less effort on the part of the programmer.

Abstract: A system is described having a JTAG diagnostic unit and a serial wire diagnostic unit. A watcher unit is connected to a data connection shared between the diagnostic units. Special patterns detected upon the shared data connection serve to switch between diagnostic modes with respective ones of the diagnostic units becoming active.

Abstract: A data processing system 2 supporting interrupt handling is provided with an interrupt controller 24. The interrupt controller is responsive to save state data when interrupt processing is commenced by pre-emption of existing processing, whether that be background processing or another interrupt. If a further interrupt is required to be executed immediately after the interrupt which triggered the pre-emption, then the speed with which interrupt processing can be started is advantageously increased if that subsequent interrupt processing is performed without restoring and then resaving the original state data. The interrupts in this arrangement can be considered to be chained together without intervening save and restore operations.

Abstract: An integrated circuit having a plurality of functional circuits interconnected via a functional bus is provided with a diagnostic bus-master circuit which uses bus transactions on the functional bus to perform diagnostic operations. These diagnostic operations can be performed in real time during normal speed operation of the integrated circuit to produce more accurate diagnostic results. The diagnostic bus-master circuit is particularly useful for reading data values from memory or writing data values to memory as part of diagnostic operations.

Abstract: A data processing system 2 is described having a central processing unit 4 and a diagnostic mechanism 10. The central processing unit 4 is switchable into a power-down mode from which it may resume into a normal operation mode. When the central processing unit 4 resumes into the normal operation mode, execution of program instructions is inhibited by the diagnostic mechanism 10 to allow the diagnostic mechanism to be appropriately programmed such that the immediate power-up code and operations can be properly diagnosed. The requirement to prevent program instruction execution on power-up is programmed by writing to a latch 16 within the diagnostic mechanism 10 prior to the power-down. The prevention of program execution may be achieved, for example, by generation of a halt request or by extending the time period for which the central processing unit 4 is held in reset following power-up.

Abstract: A direct memory access controller for controlling data transfer between a plurality of data sources and a plurality of data destinations is disclosed. The plurality of data sources and data destinations communicate with the direct memory access controller via a plurality of channels, the direct memory access controller further communicates with a memory and a processor. The memory stores two sets of control data for each of the plurality of channels and for the processor. The direct memory access controller is responsive to a data transfer request received from one of said plurality of channels or from said processor to access one set of said corresponding control data stored in said memory, said direct memory access performing at least a portion of said data transfer requested in dependence upon said accessed control data.

Abstract: An integrated circuit is provided with diagnostic circuitry, such as serial scan chains or debug bus access circuits, with which communication is established using an interface circuit coupled with a bi-directional serial link to an external diagnostic device. The bi-directional serial link carries both data and control signals.

Abstract: Following execution of a subroutine, a return instruction is executed having an address as an input operand thereto. This input operand is compared with one or more predetermined values to detect a match and the return instruction response is selected in dependence upon whether or not a match is detected. Thus, the return address value can be used to invoke differing return instruction responses, such as an exception return response or a procedure return response. The one or more predetermined addresses may be conveniently allocated to the highest memory addresses within the memory map.

Abstract: The present invention provides a breakpoint logic unit, debug logic and breakpoint method for a data processing apparatus. The breakpoint logic unit comprises a value storage operable to store data indicative of a selected value for an operational characteristic of the data processing apparatus, and comparator logic operable to compare the selected value with a value of the operational characteristic as generated by the data processing apparatus. The comparator logic then generates at least one result signal indicative of a match between that value and the selected value.

Abstract: A data processor 2 has privilege levels associated with it including a user level and a privileged level. The processor 2 also has multiple stack memories which can be used including one or more process stacks, a main stack and a deep stack. The stack memory to be used is de-coupled from the privilege level. An activation level state variable tracking the number of pending exceptions is held by the processor and used to modify which stack memory stores pending state values when an exception occurs. If the system is at a base level of activation, corresponding to currently no pending exceptions, then when an exception occurs the current state data is saved on the process stack with the main stack being available for the exception handling code. Particular exceptions can be flagged as requiring use of a deep stack rather than either the process stack or the main stack.

Abstract: An integrated circuit is provided with a diagnostic data capture and output system in the form of a diagnostic data capture circuit which captures a data word and a context word from a bus. The bus may be the functional bus connecting functional circuits within the integrated circuit or a dedicated bus linking one or more functional circuits directly to the diagnostic data capture circuit. The diagnostic data captured is buffered within a first-in-first-out buffer and then serialised for output. The diagnostic data fields also include a time value indicative of the time at which the diagnostic data field concerned was captured and whether any diagnostic data fields have failed to be captured.

Abstract: Within a system-on-chip device 2 having multiple processing circuits 4, 6, 8, one processing circuit 4 may serve to perform diagnostic operations upon another processing circuit 8 by accessing diagnostic data relating to that other circuit. Thus, one processor may, for example, control and perform halting mode type diagnostic or code profiling upon another.

Abstract: A system is described having a JTAG diagnostic unit 2 and a serial wire diagnostic unit 4. A watcher unit 6 is connected to a data connection 14 shared between the diagnostic units 2, 4. Special patterns detected upon the shared data connection 14 serve to switch between diagnostic modes with respective ones of the diagnostic units 2, 4 becoming active.

Abstract: A method and data processing apparatus for remapping selected data access requests issued by a processor for accessing data items stored on a ROM.

Abstract: A system-on-chip integrated circuit 2 is provided with multiple data processing circuits 4, 6, 8 each with an associated diagnostic interface circuit 16, 18, 20 connected via a diagnostic transaction bus 14 to a diagnostic transaction master circuit 12. The diagnostic master transaction circuit 12 issues diagnostic transaction requests to the diagnostic interface circuits 16, 18, 20. If the associated data processing circuits 4, 6, 8 are powered-down, or otherwise non responsive, then the diagnostic interface circuit 16, 18, 20 returns a diagnostic bus transaction error signal to the diagnostic transaction master circuit 12. A sticky-bit latch 30 within each diagnostic interface circuit 16, 18, 20 serves to record a power-down event and force generation of the diagnostic bus transaction error signal until that sticky bit is cleared by the diagnostic mechanisms.

Abstract: A data processing system 2 having a nested interrupt controller 24 supports nested active interrupts. The priority levels associated with different interrupts are alterable (possibly programmable) whilst the system is running. In order to prevent problems associated with priority inversions within nested interrupts, the nested interrupt controller when considering whether a pending interrupt should pre-empt existing active interrupts, compares the priority of the pending interrupt with the highest priority of any of the currently active interrupts that are nested together.