Patents by Inventor Paul M. Harvey

Paul M. Harvey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210232706
    Abstract: Online consumption data may be secured by receiving data associated with first online interactions actually performed during a predetermined time period, generating, via a machine learning model for each of a plurality of different personas, data associated with second online interactions that simulate Internet traffic, selecting a plurality of the received data associated with the first online interactions that matches the generated data associated with the second online interactions of one or more of the personas, replacing the generated data associated with the second online interactions of the one or more personas with the selected data, and outputting the one or more personas with the replaced data.
    Type: Application
    Filed: January 22, 2021
    Publication date: July 29, 2021
    Inventors: Jonathon C. Peruski, Bonnie E. Harvey, Xuyao Jiang, Frank E. Pecjak, Paul M. Deitrick
  • Patent number: 9456506
    Abstract: A mechanism is provided for packaging a multiple socket, one-hop symmetric multiprocessor topology. The mechanism connects each of a first plurality of processor modules to a first multiple-socket planar via a respective one of a first plurality of land grid array (LGA) connectors. The mechanism connects the first multiple-socket planar to a first side of a redistribution card via a second plurality of LGA connectors. The mechanism connects each of a second plurality of processor modules to a second multiple-socket planar via a respective one of a third plurality of LGA connectors. The mechanism connects the second multiple-socket planar to a second side of the redistribution card via a fourth plurality of LGA connectors.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: September 27, 2016
    Assignee: International Business Machines Corporation
    Inventors: John L. Colbert, Daniel M. Dreps, Paul M. Harvey, Rohan U. Mandrekar
  • Patent number: 9445507
    Abstract: A mechanism is provided for packaging a multiple socket, one-hop symmetric multiprocessor topology. The mechanism connects each of a first plurality of processor modules to a first multiple-socket planar via a respective one of a first plurality of land grid array (LGA) connectors. The mechanism connects the first multiple-socket planar to a first side of a redistribution card via a second plurality of LGA connectors. The mechanism connects each of a second plurality of processor modules to a second multiple-socket planar via a respective one of a third plurality of LGA connectors. The mechanism connects the second multiple-socket planar to a second side of the redistribution card via a fourth plurality of LGA connectors.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: September 13, 2016
    Assignee: International Business Machines Corporation
    Inventors: John L. Colbert, Daniel M. Dreps, Paul M. Harvey, Rohan U. Mandrekar
  • Publication number: 20150271926
    Abstract: A mechanism is provided for packaging a multiple socket, one-hop symmetric multiprocessor topology. The mechanism connects each of a first plurality of processor modules to a first multiple-socket planar via a respective one of a first plurality of land grid array (LGA) connectors. The mechanism connects the first multiple-socket planar to a first side of a redistribution card via a second plurality of LGA connectors. The mechanism connects each of a second plurality of processor modules to a second multiple-socket planar via a respective one of a third plurality of LGA connectors. The mechanism connects the second multiple-socket planar to a second side of the redistribution card via a fourth plurality of LGA connectors.
    Type: Application
    Filed: June 5, 2015
    Publication date: September 24, 2015
    Inventors: John L. Colbert, Daniel M. Dreps, Paul M. Harvey, Rohan U. Mandrekar
  • Publication number: 20150177794
    Abstract: A mechanism is provided for packaging a multiple socket, one-hop symmetric multiprocessor topology. The mechanism connects each of a first plurality of processor modules to a first multiple-socket planar via a respective one of a first plurality of land grid array (LGA) connectors. The mechanism connects the first multiple-socket planar to a first side of a redistribution card via a second plurality of LGA connectors. The mechanism connects each of a second plurality of processor modules to a second multiple-socket planar via a respective one of a third plurality of LGA connectors. The mechanism connects the second multiple-socket planar to a second side of the redistribution card via a fourth plurality of LGA connectors.
    Type: Application
    Filed: December 20, 2013
    Publication date: June 25, 2015
    Applicant: International Business Machines Corporation
    Inventors: John L. Colbert, Daniel M. Dreps, Paul M. Harvey, Rohan U. Mandrekar
  • Patent number: 8791372
    Abstract: A device and/or apparatus having plated through holes (PTHs) which are coated to reduce impedance discontinuity in electronic packages. PTH vias are imbedded in the core of a printed circuit board comprising a core layer, a plurality of buildup layers, a plurality of micro-vias, and a plurality of traces. Traces electrically interconnect each of the micro-vias to PTH vias, forming an electrically conductive path. PTHs are coated with a magnetic metal material, such as nickel, to increase the internal and external conductance of the PTHs, thereby providing decreased impedance discontinuity of the signals in electronic packages.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: July 29, 2014
    Assignee: International Business Machines Corporation
    Inventors: Paul M. Harvey, Douglas O. Powell, Wolfgang Sauter, Yaping Zhou
  • Patent number: 8631706
    Abstract: One or more decoupling capacitors are coupled to a low inductance mount that is connected to the bottom layer of a printed circuit board (PCB) on which a semiconductor module is mounted. The low inductance mount includes a magnetic planar structure with vias that are coupled to the one or more decoupling capacitors and to like vias positioned on the PCB.
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: January 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Nickolaus J Gruendler, Paul M Harvey, Tae Hong Kim, Sang Y Lee, Michael J Shapiro
  • Patent number: 8440917
    Abstract: A method, system and apparatus for coating plated through holes (PTHs) to reduce impedance discontinuity in electronic packages. PTH vias are imbedded in the core of a printed circuit board comprising a core layer, a plurality of buildup layers, a plurality of micro-vias, and a plurality of traces. Traces electrically interconnect each of the micro-vias to PTH vias, forming an electrically conductive path. PTHs are coated with a magnetic metal material, such as nickel, to increase the internal and external conductance of the PTHs, thereby providing decreased impedance discontinuity of the signals in electronic packages.
    Type: Grant
    Filed: November 19, 2007
    Date of Patent: May 14, 2013
    Assignee: International Business Machines Corporation
    Inventors: Paul M. Harvey, Douglas O. Powell, Wolfgang Sauter, Yaping Zhou
  • Publication number: 20130075148
    Abstract: A device and/or apparatus having plated through holes (PTHs) which are coated to reduce impedance discontinuity in electronic packages. PTH vias are imbedded in the core of a printed circuit board comprising a core layer, a plurality of buildup layers, a plurality of micro-vias, and a plurality of traces. Traces electrically interconnect each of the micro-vias to PTH vias, forming an electrically conductive path. PTHs are coated with a magnetic metal material, such as nickel, to increase the internal and external conductance of the PTHs, thereby providing decreased impedance discontinuity of the signals in electronic packages.
    Type: Application
    Filed: March 22, 2012
    Publication date: March 28, 2013
    Applicant: IBM CORPORATION
    Inventors: Paul M. Harvey, Douglas O. Powell, Wolfgang Sauter, Yaping Zhou
  • Patent number: 8338949
    Abstract: A system to improve core package connections may include ball grid array pads, and a ball grid array. The system may also include connection members of the ball grid array conductively connected to respective ball grid array pads. The system may further include magnetic underfill positioned adjacent at least some of the connection members and respective ball grid array pads to increase respective connection members' inductance.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: December 25, 2012
    Assignee: International Business Machines Corporation
    Inventors: Paul M. Harvey, Colm B. O'Reilly, Samuel W. Yang, Yaping Zhou
  • Patent number: 8222739
    Abstract: A system to improve core package connections may include ball grid array pads, and a ball grid array. The system may also include connection members of the ball grid array conductively connected to respective ball grid array pads. The system may further include magnetic underfill positioned adjacent at least some of the connection members and respective ball grid array pads to increase respective connection members' inductance.
    Type: Grant
    Filed: December 19, 2009
    Date of Patent: July 17, 2012
    Assignee: International Business Machines Corporation
    Inventors: Paul M. Harvey, Colm B. O'Reilly, Samuel W. Yang, Yaping Zhou
  • Publication number: 20120175763
    Abstract: An integrated circuit package includes a package core and a primary circuitry chip mounted on the package core. The primary circuitry chip has an active surface in which the core circuitry is fabricated. The active surface of the primary circuitry chip faces the package core and includes contacts. The integrated circuit package further includes an auxiliary circuit chip assembled to the package core and having contacts facing and electrically connected to the contacts of the primary circuitry chip.
    Type: Application
    Filed: January 6, 2011
    Publication date: July 12, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: PAUL M. HARVEY, ROHAN U. MANDREKAR, SAMUEL W. YANG, YAPING ZHOU
  • Publication number: 20120138349
    Abstract: A system to improve core package connections may include ball grid array pads, and a ball grid array. The system may also include connection members of the ball grid array conductively connected to respective ball grid array pads. The system may further include magnetic underfill positioned adjacent at least some of the connection members and respective ball grid array pads to increase respective connection members' inductance.
    Type: Application
    Filed: February 8, 2012
    Publication date: June 7, 2012
    Applicant: International Business Machines Corporation
    Inventors: Paul M. Harvey, Colm B. O'Reilly, Samuel W. Yang, Yaping Zhou
  • Publication number: 20120020042
    Abstract: One or more decoupling capacitors are coupled to a low inductance mount that is connected to the bottom layer of a printed circuit board (PCB) on which a semiconductor module is mounted. The low inductance mount includes a magnetic planar structure with vias that are coupled to the one or more decoupling capacitors and to like vias positioned on the PCB.
    Type: Application
    Filed: July 21, 2010
    Publication date: January 26, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nickolaus J. Gruendler, Paul M. Harvey, Tae Hong Kim, Sang Y. Lee, Michael J. Shapiro
  • Publication number: 20110147044
    Abstract: A system to improve core package connections may include ball grid array pads, and a ball grid array. The system may also include connection members of the ball grid array conductively connected to respective ball grid array pads. The system may further include magnetic underfill positioned adjacent at least some of the connection members and respective ball grid array pads to increase respective connection members' inductance.
    Type: Application
    Filed: December 19, 2009
    Publication date: June 23, 2011
    Applicant: International Business Machines Corporation
    Inventors: Paul M. Harvey, Colm B. O'Reilly, Samuel W. Yang, Yaping Zhou
  • Patent number: 7911049
    Abstract: An electrically optimized and structurally protected micro via structure for high speed signals in multilayer interconnection substrates is provided. The via structure eliminates the overlap of a contact with the reference planes to thereby reduce the via capacitance and thus, the via impedance mismatch in the via structure. As a result, the via structure is electrically optimized. The via structure further comprises one or more floating support members placed in close proximity to the via within a via clearance area between the via and the reference planes. The floating support members are “floating” in the sense that they are not in electrical contact with either the via or the reference planes. Thus, they are not provided for purposes of signal propagation but only for structural support. The floating support members may be connected to one another by way of one or more microvia structures.
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: March 22, 2011
    Assignee: International Business Machines Corporation
    Inventors: Paul M. Harvey, Kazushige Kawasaki, Gen Yamada
  • Patent number: 7687391
    Abstract: An electrically optimized and structurally protected micro via structure for high speed signals in multilayer interconnection substrates is provided. The via structure eliminates the overlap of a contact with the reference planes to thereby reduce the via capacitance and thus, the via impedance mismatch in the via structure. As a result, the via structure is electrically optimized. The via structure further comprises one or more floating support members placed in close proximity to the via within a via clearance area between the via and the reference planes. The floating support members are “floating” in the sense that they are not in electrical contact with either the via or the reference planes. Thus, they are not provided for purposes of signal propagation but only for structural support. The floating support members may be connected to one another by way of one or more microvia structures.
    Type: Grant
    Filed: September 27, 2006
    Date of Patent: March 30, 2010
    Assignee: International Business Machines Corporation
    Inventors: Paul M. Harvey, Kazushige Kawasaki, Gen Yamada
  • Publication number: 20090302874
    Abstract: A method and apparatus for probing a circuit board, is provided. One implementation involves a signal probe including a tip having a plurality of strands of flexible conductive material surrounding the tip, the strands extending out from the tip to provide multiple points of contact with the rim of a via or a conductive barrel of the via when the tip is inserted into the via, the probe tip and probe strands being made of same conductive material; such that aligning the signal probe with the via for engaging the probe tip strands with the via, and inserting the tip into the via, causes bending and flexing of the strands for making contact with a conductor on a top rim of the barrel and inside an inner wall of the barrel.
    Type: Application
    Filed: June 6, 2008
    Publication date: December 10, 2009
    Applicant: International Business Machines Corporation
    Inventors: Paul M. Harvey, Samuel W. Yang, Yaping Zhou
  • Publication number: 20090126983
    Abstract: A method, system and apparatus for coating plated through holes (PTHs) to reduce impedance discontinuity in electronic packages. PTH vias are imbedded in the core of a printed circuit board comprising a core layer, a plurality of buildup layers, a plurality of micro-vias, and a plurality of traces. Traces electrically interconnect each of the micro-vias to PTH vias, forming an electrically conductive path. PTHs are coated with a magnetic metal material, such as nickel, to increase the internal and external conductance of the PTHs, thereby providing decreased impedance discontinuity of the signals in electronic packages.
    Type: Application
    Filed: November 19, 2007
    Publication date: May 21, 2009
    Inventors: Paul M. Harvey, Douglas O. Powell, Wolfgang Sauter, Yaping Zhou
  • Patent number: 7492570
    Abstract: Systems and methods for reducing switching noise in an integrated circuit. In one embodiment, decoupling capacitors are connected to the integrated circuit from the underside of the substrate on which the integrated circuit die is manufactured. The decoupling capacitors are positioned with a higher concentration in the “hot spot” areas of the integrated circuit instead of being evenly distributed. In one embodiment, the decoupling capacitors and the corresponding hole(s) in a circuit board on which the integrated circuit is mounted are positioned so that the circuit board provides support for the central portion of the integrated circuit and thereby prevents the integrated circuit from flexing away from the heat sink/spreader. In one embodiment, the concentration of vias connecting the different ground planes and/or power planes within the integrated circuit is higher in hot spots than in other areas.
    Type: Grant
    Filed: April 13, 2005
    Date of Patent: February 17, 2009
    Assignees: Kabushiki Kaisha Toshiba, International Business Machines Corporation
    Inventors: Eiichi Hosomi, Paul M. Harvey