Patents by Inventor Paul P. Viallon

Paul P. Viallon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4680733
    Abstract: A serdes device includes circuitry for loading or reading bit configurations into or out of strings of latches of variable length nk+r, where n is the number of bits in a byte, k is the number of whole bytes and r is the number of residual bits, with r being smaller than n.Under the control of a service processor (8), there is formed a ring comprised of the latches of the serializer/deserializer register (14), the latches of the string considered (3 or 4) and a selected number (n-r) of latches of an extension register (16). The bytes to be loaded are sequentially sent to register (14), starting with the byte that contains the residual bits, and n bits are shifted out after loading each successive byte, so that after k+1 shifts the desired configuration will be contained in the string. For reading the contents of a string (for example, string 3), n bits are shifted, register (14) is read out, then k shifts of n bits each are performed, with register (14) being read out after each shift.
    Type: Grant
    Filed: October 29, 1984
    Date of Patent: July 14, 1987
    Assignee: International Business Machines Corporation
    Inventors: Guy G. Duforestel, Michel A. Lechaczynski, Clement Y. Poiraud, Paul P. Viallon