Abstract: A method including filling etched moats with a first dielectric layer and layer of polycrystalline material and planarizing. A second dielectric layer is formed on the first polycrystalline layer and a second layer of polycrystalline is formed on the second dielectric layer to form a handle. The starting material is then thinned to produce the dielectric isolated islands. Device forming steps are then performed. Finally, the handle is removed leaving a wafer having a thickness defined by the planarized surface of the first polycrystalline layer and the top surface of the first wafer.

Abstract: A process including bonding a first device wafer to a handle wafer by an intermediate bonding oxide layer and thinning the device wafer to not greater than 7 mils. An epitaxial device layer of under 1 mil may be added. Device formation steps are performed on a first surface of the first device wafer. This is followed by removing the handle wafer to produce a resulting wafer having substantially the thickness of the first device layer. To produce a silicon on insulator (SOI), a third device wafer is bonded to the first surface of the first device wafer by the intermediate oxide layer and the third wafer is thinned to not greater than 40 microns. The first and third device wafers form the resulting SOI wafer.

Abstract: Single crystal dielectrically isolated islands are formed providing a substantially non-reflective or indentured silicon surface before the application of the dielectric isolation layer and the polycrystalline support. Thin film resistor material is formed and delineated on an insulative layer over the single crystal island juxtaposed to the substantially non-reflective bottom dielectric isolation. The thin film resistive layer is trimmed using a laser.

Abstract: Plane indicating moats are formed extending through an epitaxial layer into a substrate simultaneous with the formation of the isolation moats which terminate within the epitaxial layer. The substrate is ground to a predetermined thickness after formation of the dielectric isolation and support structure. The composite structure is inserted in an etchant with conditions set to electrochemically etch only the substrate. The exposed plane indicating moats are used as a reference for a final polishing step.