Patents by Inventor Paul Saunier

Paul Saunier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4599790
    Abstract: Using the present invention, a gate for a MESFET may be fabricated having a minimum gate length while having a low resistance gate. In addition, the present invention provides a method for forming a gate and gate recess which are perfectly aligned which is the optimal structure for high frequency power MESFETs. A two layer masking layer is fabricated having a first layer which may be etched uniformly and a second layer of lithographic material which may be photolithographic material such as AZ resist. A gate opening is patterned in the photoresist material and a metal such as gold is deposited by evaporation from acute angles on opposite sides of the gate opening in the resist. The deposited metal serves as a mask which covers all but a very small portion of the opening in the photoresist. The silicon nitride layer is then etched to form a gate opening and gate recess.
    Type: Grant
    Filed: January 30, 1985
    Date of Patent: July 15, 1986
    Assignee: Texas Instruments Incorporated
    Inventors: Bumman Kim, Paul Saunier
  • Patent number: 4558337
    Abstract: A multiple high electron mobility transistor structure without inverted heterojunctions is disclosed. Multiple normal heterojunctions of doped aluminum gallium arsenide grown on gallium arsenide without alternating inverted heterojunctions of gallium arsenide grown on doped aluminum gallium arsenide is achieved by grading undoped aluminum gallium arsenide from the doped aluminum gallium arsenide to the gallium arsenide to avoid an inverted heterojunction.
    Type: Grant
    Filed: May 30, 1984
    Date of Patent: December 10, 1985
    Assignee: Texas Instruments Inc.
    Inventors: Paul Saunier, Hung-Dah Shih