Abstract: A method is provided for fabricating piezoelectric plates. A sacrificial layer is formed overlying a growth substrate. A template layer, with openings exposing sacrificial layer surfaces, is formed over the sacrificial layer. An adhesion layer/first electrode stack is selectively deposited in the openings overlying the sacrificial layer surfaces, and a piezoelectric material formed in the openings overlying the stack. Then, a second electrode is formed overlying the piezoelectric material. Using the second electrode as a hardmask, the piezoelectric material is etched to form polygon-shaped structures, such as disks, attached to the sacrificial layer surfaces. After removing the template layer and annealing, the polygon-shaped structures are separated from the sacrificial layer. With the proper choice of growth substrate material, the annealing can be performed at a relatively high temperature.

Abstract: A method is provided for fabricating piezoelectric plates. A sacrificial layer is formed overlying a growth substrate. A template layer, with openings exposing sacrificial layer surfaces, is formed over the sacrificial layer. An adhesion layer/first electrode stack is selectively deposited in the openings overlying the sacrificial layer surfaces, and a piezoelectric material formed in the openings overlying the stack. Then, a second electrode is formed overlying the piezoelectric material. Using the second electrode as a hardmask, the piezoelectric material is etched to form polygon-shaped structures, such as disks, attached to the sacrificial layer surfaces. After removing the template layer and annealing, the polygon-shaped structures are separated from the sacrificial layer. With the proper choice of growth substrate material, the annealing can be performed at a relatively high temperature.

Abstract: A method is provided for fabricating a thin-film electronic device employing a piezoelectric plate. The method provides a plurality of piezoelectric plates, and a substrate with electronic devices, each electronic device including a top surface well. A piezoelectric plate suspension is formed and flowed over the substrate. In response to the piezoelectric plate suspension flow, piezoelectric plates are captured in the top surface wells. The electric device top surface wells have well bottom surfaces, with bottom electrical contacts formed on the bottom surfaces. Thus, the capture of a piezoelectric plate in a top surface well entails interfacing a piezoelectric plate electrode, either the first electrode or the second electrode, to the bottom electrical contact. Subsequent to capturing the piezoelectric plates in the top surface wells, a thin-film process forms a conductive line overlying the exposed piezoelectric device electrode (i.e., the electrode not connected to the bottom electrical contact).

Abstract: A method is provided for fabricating piezoelectric plates. A sacrificial layer is formed overlying a growth substrate. A template layer, with openings exposing sacrificial layer surfaces, is formed over the sacrificial layer. An adhesion layer/first electrode stack is selectively deposited in the openings overlying the sacrificial layer surfaces, and a piezoelectric material formed in the openings overlying the stack. Then, a second electrode is formed overlying the piezoelectric material. Using the second electrode as a hardmask, the piezoelectric material is etched to form polygon-shaped structures, such as disks, attached to the sacrificial layer surfaces. After removing the template layer and annealing, the polygon-shaped structures are separated from the sacrificial layer. With the proper choice of growth substrate material, the annealing can be performed at a relatively high temperature.

Abstract: A method is provided for fabricating piezoelectric plates. A sacrificial layer is formed overlying a growth substrate. A template layer, with openings exposing sacrificial layer surfaces, is formed over the sacrificial layer. An adhesion layer/first electrode stack is selectively deposited in the openings overlying the sacrificial layer surfaces, and a piezoelectric material formed in the openings overlying the stack. Then, a second electrode is formed overlying the piezoelectric material. Using the second electrode as a hardmask, the piezoelectric material is etched to form polygon-shaped structures, such as disks, attached to the sacrificial layer surfaces. After removing the template layer and annealing, the polygon-shaped structures are separated from the sacrificial layer. With the proper choice of growth substrate material, the annealing can be performed at a relatively high temperature.

Abstract: A method is provided for fabricating a thin-film electronic device employing a piezoelectric plate. The method provides a plurality of piezoelectric plates, and a substrate with electronic devices, each electronic device including a top surface well. A piezoelectric plate suspension is formed and flowed over the substrate. In response to the piezoelectric plate suspension flow, piezoelectric plates are captured in the top surface wells. The electric device top surface wells have well bottom surfaces, with bottom electrical contacts formed on the bottom surfaces. Thus, the capture of a piezoelectric plate in a top surface well entails interfacing a piezoelectric plate electrode, either the first electrode or the second electrode, to the bottom electrical contact. Subsequent to capturing the piezoelectric plates in the top surface wells, a thin-film process forms a conductive line overlying the exposed piezoelectric device electrode (i.e., the electrode not connected to the bottom electrical contact).

Abstract: A video display is provided with a planar piezoelectric transmitter to transmit ultrasound signals, and a display panel including a plurality of pixels. Each pixel has a data interface to accept a video signal with a variable voltage associated with a range of light intensity values, and to supply a touch signal with a variable voltage derived from a range of reflected ultrasound signal energies. Each pixel is made up of a light device to supply light with an intensity responsive to the video signal voltage, and a storage capacitor to maintain a video signal voltage between refresh cycles. A piezoelectric transducer accepts a reflected ultrasound signal energy and maintains a touch signal voltage between refresh cycles. In one aspect, the storage capacitor and the piezoelectric transducer are the same device. The light device may be a liquid crystal (LC) layer or a light emitting diode.

Abstract: A piezo thin-film diode (piezo-diode) cantilever microelectromechanical system (MEMS) and associated fabrication processes are provided. The method deposits thin-films overlying a substrate. The substrate can be made of glass, polymer, quartz, metal foil, Si, sapphire, ceramic, or compound semiconductor materials. Amorphous silicon (a-Si), polycrystalline Si (poly-Si), oxides, a-SiGe, poly-SiGe, metals, metal-containing compounds, nitrides, polymers, ceramic films, magnetic films, and compound semiconductor materials are some examples of thin-film materials. A cantilever beam is formed from the thin-films, and a diode is embedded with the cantilever beam. The diode is made from a thin-film shared in common with the cantilever beam. The shared thin-film may a film overlying a cantilever beam top surface, a thin-film overlying a cantilever beam bottom surface, or a thin-film embedded within the cantilever beam.

Abstract: A method is provided for concurrently forming MP-TFTs and P-TFTs. Generally, the method comprises: forming a P-TFT having source/drain (S/D) regions, an intervening channel region, and a gate, all in a first horizontal plane; and simultaneously forming a MP-TFT having a first gate in the first horizontal plane and at least one S/D region in a second horizontal plane, overlying the first horizontal plane. The vertical TFT (V-TFT) is an MP-TFT having vertical first gate sidewalls and a vertical channel region overlying a gate sidewall. The dual-gate TFT (DG-TFT) is an MP-TFT having a bottom gate, first and second S/D regions with top surfaces, an intervening channel region with a top surface, and a second, top gate with a bottom surface, all in a second horizontal plane, overlying the first horizontal plane.

Abstract: A digital-to-time converter (DTC) is provided, made from a plurality of series-connected cells. Each cell has an input interface to accept a signal, a control interface to accept a digital command, a delayed signal path, a minimum delay signal path, and an output interface. The signal path is selected in response to the command. The time delay associated with the delayed signal path of each cell can be varied, so that the plurality of series-connected cells is able to provide a large range of delay combinations. For example, if there are n series-connected cells, then the jth series-connected cell, where j varies from 1 to n, conducts the signal through 2j MOS gates in the delayed signal path. Assuming a digital control word with n bit places, the jth series-connected cell accepts the jth bit place of the control word to select a delay path.

Abstract: A method of fabricating local interconnect on a silicon-germanium 3D CMOS includes fabricating an active silicon CMOS device on a silicon substrate. An insulator layer is deposited on the silicon substrate and a seed window is opened through the insulator layer to the silicon substrate and to a silicon CMOS device gate. A germanium thin film is deposited on the insulator layer and into windows, forming a contact between the germanium thin film and the silicon device. The germanium thin film is encapsulated in a dielectric material. The wafer is heated at a temperature sufficient to flow the germanium, while maintaining the other layers in a solid condition. The wafer is cooled to solidify the germanium as single crystal germanium and as polycrystalline germanium, which provides local interconnects. Germanium CMOS devices may be fabricated on the single crystal germanium thin film.

Abstract: A sidewall gate thin-film transistor (TFT) and associated fabrication method are provided. The method provides a substrate with a surface and forms a surface-normal feature. The surface-normal feature is normal with respect to the substrate surface, with a sidewall made from an electrical insulator. An active silicon (Si) layer is formed overlying the surface-normal feature, with a channel overlying the surface-normal feature sidewall. A gate insulator overlies the channel, and a sidewall gate overlies the gate insulator. More specifically, the gate insulator is formed from conformally depositing an electrical insulator layer overlying the active Si layer. The gate electrode layer is conformally deposited overlying the gate insulator layer and anisotropically etched, leaving a gate electrode sidewall adjacent to the gate insulator layer overlying the channel.

Abstract: A four-transistor Schmitt trigger inverter is provided. The Schmitt trigger inverter is made from an n-channel MOS (NMOS) dual-gate thin-film transistor (DG-TFT) and a p-channel MOS (PMOS) DG-TFT, both DG-TFTs having a top gate, a back gate, and source/drain regions. A (conventional) NMOS TFT has a gate connected to an NMOS DG-TFT first S/D region and a PMOS DG-TFT first S/D region. The NMOS TFT also has a first S/D region connected to the NMOS DG-TFT back gate and the PMOS DG-TFT back gate. A (conventional) PMOS TFT has a gate connected to the NMOS TFT gate, and a first S/D region connected to the NMOS TFT first S/D region.

Abstract: A two-transistor tri-state inverter is provided, made from a NMOS dual-gate thin-film transistor (DG-TFT) having a top gate, a back gate, and source/drain regions. A PMOS DG-TFT also has a top gate, a back gate, and S/D regions, and the NMOS first S/D region is connected to a PMOS first S/D region. The NMOS top gate is connected to an input signal (Vin), the back gate is connected to a control signal (Vb), the first S/D region supplies an output signal (Vout), and a second S/D region is connected to a reference voltage. The PMOS top gate is connected to the input signal, the back gate is connected to an inverted control signal (?Vb), and a second S/D region is connected to a supply voltage having a higher voltage than the reference voltage.

Abstract: A dual-gate thin film transistor (DG-TFT) and associated fabrication method are provided. The method comprises: forming a first (back) gate in a first horizontal plane; forming source/drain (S/D) regions and an intervening channel region in a second horizontal plane, overlying the first plane; and, forming a second (top) gate in a third horizontal plane, overlying the second plane. The S/D regions and intervening channel region have a combined length, smaller than the length of the first gate. A substrate insulating layer is formed over the substrate, made from a material such as SiO2. A first gate insulation layer is formed over the first gate. Amorphous silicon (a-Si) is deposited over the first gate insulation layer and crystallized. The S/D and channel regions are formed from the crystallized Si layer. A second gate oxide layer is formed over the channel region.

Abstract: A dual-gate thin-film transistor (DG-TFT) voltage storage circuit is provided. The circuit includes a voltage storage element, a DG-TFT having a first source/drain (S/D) connected to a data line, a top gate connected to a first gate line, a second S/D region connected to the voltage storage element, and a bottom gate connected to a bias line. In one aspect, the circuit further includes a voltage shifter having an input connected to the first gate line and an output to supply a bias voltage on the bias line. Examples of a voltage storage element include a capacitor, a liquid crystal (LC) pixel, and a light emitting diode (LED) pixel.

Abstract: A vertical thin-film transistor (V-TFT) is provided along with a method for forming the V-TFT. The method comprises: providing a substrate made from a material such as Si, quartz, glass, or plastic; conformally depositing an insulating layer overlying the substrate; forming a gate, having sidewalls and a thickness, overlying a substrate insulation layer; forming a gate oxide layer overlying the gate sidewalls, and a gate insulation layer overlying the gate top surface; etching the exposed substrate insulation layer; forming a first source/drain region overlying the gate insulation layer; forming a second source/drain region overlying the substrate insulation layer, adjacent a first gate sidewall; and, forming a channel region overlying the first gate sidewall with a channel length about equal to the thickness of the gate, interposed between the first and second source/drain regions.

Abstract: A vertical thin-film transistor (V-TFT) is provided along with a method for forming the V-TFT. The method comprises: providing a substrate made from a material such as Si, quartz, glass, or plastic; conformally depositing an insulating layer overlying the substrate; forming a gate, having sidewalls and a thickness, overlying a substrate insulation layer; forming a gate oxide layer overlying the gate sidewalls, and a gate insulation layer overlying the gate top surface; etching the exposed substrate insulation layer; forming a first source/drain region overlying the gate insulation layer; forming a second source/drain region overlying the substrate insulation layer, adjacent a first gate sidewall; and, forming a channel region overlying the first gate sidewall with a channel length about equal to the thickness of the gate, interposed between the first and second source/drain regions.

Abstract: A method is provided for concurrently forming MP-TFTs and P-TFTs. Generally, the method comprises: forming a P-TFT having source/drain (S/D) regions, an intervening channel region, and a gate, all in a first horizontal plane; and simultaneously forming a MP-TFT having a first gate in the first horizontal plane and at least one S/D region in a second horizontal plane, overlying the first horizontal plane. The vertical TFT (V-TFT) is an MP-TFT having vertical first gate sidewalls and a vertical channel region overlying a gate sidewall. The dual-gate TFT (DG-TFT) is an MP-TFT having a bottom gate, first and second S/D regions with top surfaces, an intervening channel region with a top surface, and a second, top gate with a bottom surface, all in a second horizontal plane, overlying the first horizontal plane.

Abstract: A vertical thin-film transistor (V-TFT) inverter circuit and a method for forming a multi-planar layout TFT inverter circuit have been provided. The method comprising: forming a P-channel TFT with a gate, a first source/drain (S/D) region in a first horizontal plane, and a second S/D region in a second horizontal plane, different than the first horizontal plane; and, forming an N-channel TFT, adjacent the P-channel TFT, with a gate, a third S/D region in a third horizontal plane, and a fourth S/D region in the second horizontal plane, different than the third horizontal plane. Forming a P-channel TFT includes forming a P-channel top-drain vertical TFT (TDV-TFT), and forming an N-channel TFT includes forming an N-channel TDV-TFT.