Abstract: Through substrate vias (TSVs) are provided after substantially all high temperature operations needed to form a device region (26) of a first thickness (27) proximate the front surface (23) of a substrate wafer (20, 20?) by: (i) from the front surface (23), forming comparatively shallow vias (30, 30?) of a first aspect ratio containing first conductors (36, 36?) extending preferably through the first thickness (27) but not through the initial wafer (20) thickness (21), (ii) removing material (22?) from the rear surface (22) to form a modified wafer (20?) of smaller final thickness (21?) with a new rear surface (22?), and (iii) forming from the new rear surface (22?), much deeper vias (40, 40?) of second aspect ratios beneath the device region (26) with second conductors (56, 56?) therein contacting the first conductors (36, 36?), thereby providing front-to-back interconnections without substantially impacting wafer robustness during manufacturing and device region area.

Abstract: Through substrate vias (TSVs) are provided after substantially all high temperature operations needed to form a device region of a first thickness proximate the front surface of a substrate wafer by: (i) from the front surface, forming comparatively shallow vias of a first aspect ratio containing first conductors extending preferably through the first thickness but not through the initial wafer thickness, (ii) removing material from the rear surface to form a modified wafer of smaller final thickness with a new rear surface, and (iii) forming from the new rear surface, much deeper vias of second aspect ratios beneath the device region with second conductors therein contacting the first conductors, thereby providing front-to-back interconnections without substantially impacting wafer robustness during manufacturing and device region area. Both aspect ratios are desirably about ?40, usefully ?10 and preferably ?5.

Abstract: Through substrate vias for back-side electrical and thermal interconnections on very thin semiconductor wafers without loss of wafer mechanical strength during manufacturing are provided by: forming desired device regions with contacts on the front surface of an initially relatively thick wafer; etching via cavities partly through the wafer in the desired locations; filling the via cavities with a conductive material coupled to some device region contacts; mounting the wafer with its front side facing a support structure; thinning the wafer from the back side to expose internal ends of the conductive material filled vias; applying any desired back-side interconnect region coupled to the exposed ends of the filled vias; removing the support structure and separating the individual device or IC assemblies so as to be available for mounting on a further circuit board, tape or larger circuit.

Abstract: Through substrate vias for back-side electrical and thermal interconnections on very thin semiconductor wafers without loss of wafer mechanical strength during manufacturing are provided by: forming (101) desired device regions (21) with contacts (22) on the front surface (19) of an initially relatively thick wafer (18?); etching (104) via cavities (29) partly through the wafer (18?) in the desired locations; filling (105) the via cavities (29) with a conductive material (32) coupled to some device region contacts (22); mounting (106) the wafer (18?) with its front side (35) facing a support structure (40); thinning (107) the wafer (18?) from the back side (181) to expose internal ends (3210, 3220, 3230, 3240, etc.) of the conductive material filled vias (321, 322, 323, 324, etc.); applying (108) any desired back-side interconnect region (44) coupled to the exposed ends (3210, 3220, 3230, 3240, etc.

Abstract: Through substrate vias (TSVs) are provided after substantially all high temperature operations needed to form a device region (26) of a first thickness (27) proximate the front surface (23) of a substrate wafer (20, 20?) by: (i) from the front surface (23), forming comparatively shallow vias (30, 30?) of a first aspect ratio containing first conductors (36, 36?) extending preferably through the first thickness (27) but not through the initial wafer (20) thickness (21), (ii) removing material (22?) from the rear surface (22) to form a modified wafer (20?) of smaller final thickness (21?) with a new rear surface (22?), and (iii) forming from the new rear surface (22?), much deeper vias (40, 40?) of second aspect ratios beneath the device region (26) with second conductors (56, 56?) therein contacting the first conductors (36, 36?), thereby providing front-to-back interconnections without substantially impacting wafer robustness during manufacturing and device region area.

Abstract: A through-silicon via structure is formed by providing a substrate having a first conductive catch pad and a second conductive catch pad formed thereon. The substrate is secured to a wafer carrier. A first etch of a first type is performed on the substrate underlying each of the first and second conductive catch pads to form a first partial through-substrate via of a first diameter underlying the first conductive catch pad and a second partial through-substrate via underlying the second conductive catch pad of a second diameter that differs from the first diameter. A second etch of a second type that differs from the first type is performed to continue etching the first partial through-substrate to form equal depth first and second through-substrate vias respectively to the first and second conductive catch pads.

Abstract: 3-D ICs (18, 18?, 90) with integrated passive devices (IPDs) (38) having reduced cross-talk and high packing density are provided by stacking separately prefabricated substrates (20, 30, 34) coupled by through-substrate-vias (TSVs) (40). An active device (AD) substrate (20) has contacts on its upper portion (26). An isolator substrate (30) is bonded to the AD substrate (20) so that TSVs (4030) in the isolator substrate (30) are coupled to the contacts (26) on the AD substrate (20), and desirably has an interconnect zone (44) on its upper surface. An IPD substrate (34) is bonded to the isolator substrate (30) so that TSVs (4034) therein are coupled to the interconnect zone (44) on the isolator substrate (30) and/or TSVs (4030) therein. The IPDs (38) are formed on its upper surface and coupled by TSVs (4034, 4030) in the IPD (34) and isolator (30) substrates to devices (26) in the AD substrate (20).

Abstract: Through substrate vias for back-side electrical and thermal interconnections on very thin semiconductor wafers without loss of wafer mechanical strength during manufacturing are provided by: forming (101) desired device regions (21) with contacts (22) on the front surface (19) of an initially relatively thick wafer (18?); etching (104) via cavities (29) partly through the wafer (18?) in the desired locations; filling (105) the via cavities (29) with a conductive material (32) coupled to some device region contacts (22); mounting (106) the wafer (18?) with its front side (35) facing a support structure (40); thinning (107) the wafer (18?) from the back side (181) to expose internal ends (3210, 3220, 3230, 3240, etc.) of the conductive material filled vias (321, 322, 323, 324, etc.); applying (108) any desired back-side interconnect region (44) coupled to the exposed ends (3210, 3220, 3230, 3240, etc.

Abstract: A through-silicon via structure is formed by providing a substrate having a first conductive catch pad and a second conductive catch pad formed thereon. The substrate is secured to a wafer carrier. A first etch of a first type is performed on the substrate underlying each of the first and second conductive catch pads to form a first partial through-substrate via of a first diameter underlying the first conductive catch pad and a second partial through-substrate via underlying the second conductive catch pad of a second diameter that differs from the first diameter. A second etch of a second type that differs from the first type is performed to continue etching the first partial through-substrate to form equal depth first and second through-substrate vias respectively to the first and second conductive catch pads.

Abstract: A semiconductor device (10) is formed in a semiconductor substrate (11) that acts as a collector region. A base region (12) is formed in the semiconductor substrate (11) and an emitter region (52) is formed such that it contacts at least a portion of the base region (12). A conductive layer (28) is used to provide electrical connection to the emitter region (52). The portion of the conductive layer (28) above the emitter region (52) is counter-doped to address the problems of an interfacial oxide layer (27) that exists between the emitter region (52) and the conductive layer (28).

Abstract: A self-aligned semiconductor component (10) includes a layer (14) having two openings (36, 38) and overlying a doped region (13) in a substrate (11). One (36) of the two openings (36, 38) is used to self-align a different doped region (22) and a portion (27) of an electrode (27, 31). The electrode (27, 31) has another portion (31) overlying the self-aligned portion (27) to increase the current carrying capacity of the electrode (27, 31). A different electrode is formed in the other one (38) of the two openings (36, 38) and has a smaller current carrying capacity than the other electrode (27, 31).

Abstract: The present invention provides a method of forming a semiconductor device. A layer of photoresist is applied to a semiconductor wafer. A first mask is used to protect a first portion of the photoresist while a second portion of the photoresist is exposed. A second mask is used to expose a third portion of the photoresist wherein the third portion of the photoresist includes part of the first portion of the photoresist. The photoresist is developed to form a photoresist mask.

Abstract: An assembly is formed by coupling a plurality of semiconductor chips (26-29) to a surface of a substrate (17). An encapsulation material (22) is placed on the surface of the substrate (17) to protect the semiconductor chips (26-29) from an external environment. Material is removed from the plurality of semiconductor chips (26-29) to thin each semiconductor chip (26-29) to promote thermal conductivity.

Abstract: A technique for improving the frequency response of a semiconductor device employing silicon as the semiconductor material. Parasitic components inherent in semiconductor devices degrade the performance of these devices at higher frequencies. Typically, a parasitic capacitor includes a dielectric material sandwiched between a conductive interconnect (31A, 31B) and a substrate (10) or a bottom contact (18). Further, in the past, the thickness of this dielectric material has been similar to that of the third dielectric material (17) of the present invention. However, in the present invention the effective thickness of the dielectric material has been increased by including a first and second dielectric material (15, 16) as well as the third dielectric material (17). Increasing the thickness of the dielectric of a parasitic capacitor decreases the value of the parasitic capacitance; and therefore increases the cut-off frequency of the semiconductor device.

Abstract: An improved high frequency dielectrically isolated (DIC) transistor (100) or integrated circuit is obtained by providing a highly doped single crystal semiconductor region (112) coupled to the device reference terminal (16') and extending between front (98) and rear (61) faces of the semiconductor die. This allows the reference terminal (16', 116) to be coupled to the package ground plane without use of wire bonds, thereby lowering the common mode impedance. The desired structure is formed in connection with DIC devices (100) by etching first (66) and second (77) nested cavities into a single crystal substrate (60). The cavities (66) form protruding islands (821, 822) of single crystal semiconductor having a height (80+68) about equal the final die thickness (110) and which, after conventional DIC processing using an oxide isolation layer (86) and a poly handle (88), are exposed by grinding away the poly handle (88) to expose the highly doped, single crystal reference terminal feed-through (112).

Abstract: A protective circuit for an input to a bipolar transistor (10) capable of operating in the microwave frequency range. In a first embodiment, a polysilicon diode (24) is connected across a base-emitter junction of the bipolar transistor (10). In a second embodiment, a polysilicon resistor (38) is connected in series with an emitter of the bipolar transistor (10), and the polysilicon diode (24) is connected across the series combination of the base-emitter junction and the polysilicon resistor (38). The layout of the transistor (10) and the islands of polysilicon (23, 25) housing the diode is critical since the bipolar transistor (10) is capable of operating in the microwave frequency range. In a first layout, an island of polysilicon (25) is centered between two transistor regions (47 and 48). In an exterior diode layout, a transistor region (51) is centered between two islands of polysilicon (23 and 25).

Abstract: A MOSFET having a back-side source contact and top-side gate and drain contacts is provided by a structure comprising superposed N.sup.+, N-, P-, N.sup.+ regions arranged between top and bottom surfaces of the semiconductor die. In a preferred implementation, two trenches are etched from the top surface to the P-, N.sup.+ interface. A buried P-, N.sup.+ short is provided in one trench and a gate dielectric and gate electrode are provided over the sidewall P- region exposed in the other trench. This creates a vertical MOSFET in which the N.sup.+ substrate forms the source region shorted to the P- body region in which the channel is created by the gate. Superior performance is obtained in RF grounded-source circuit applications.

Abstract: A high frequency, low cost power semiconductor device (60) is provided by combining a semiconductor die (46) with a leadframe (10,12) having a coplanar upper surface (36) with thin external leads (18,20) and a thicker central die bond region (24) whose upper face (16) and sides (42) are covered by an encapsulation (52) but whose lower face (54) is exposed. The leadframe (10,12) desirably has an "H" pattern with the arms (18,20) extending laterally from opposed sides of the encapsulation (52) and down-formed to have their lower surfaces (62) coplanar with the exposed lower face (54) of the central die bond region (16,24) which forms the cross-bar of the "H". The leadframe is monolithic and preferably formed by skiving. The device is especially suited for surface-mounting.

Abstract: A MOSFET having a back-side source contact and top-side gate and drain contacts is provided by a structure comprising superposed N.sup.+, N-,P-, N.sup.+ regions arranged between top and bottom surfaces of the semiconductor die. In a preferred implementation, two trenches are etched from the top surface to the P-, N.sup.+ interface. A buried P-, N.sup.+ short is provided in one trench and a gate dielectric and gate electrode are provided over the sidewall P- region exposed in the other trench. This creates a vertical MOSFET in which the N.sup.+ substrate forms the source region shorted to the P- body region in which the channel is created by the gate. Superior performance is obtained in RF grounded-source circuit applications.

Abstract: Improved dielectrically isolated semiconductor structures especially suited for very high frequency bipolar transistors are produced. Recesses are formed in a (e.g., N.sup.+) single crystal semiconductor wafer, the wafer surface is coated with a dielectric, and a thick polycrystalline semiconductor layer is deposited thereon to provide a support. The single crystal wafer is back-lapped to expose dielectrically isolated N.sup.+ islands located between the original recesses. Depressions are etched in the N.sup.+ islands and the exposed surface is covered by a more lightly doped (e.g., N.sup.-) semiconductor layer which is, generally, single crystal above the N.sup.+ islands and non-single crystal therebetween, and which at least fills the depressions. The structure is then planarized (e.g., by lapping and etching) to remove this non-single crystal material and give isolated single crystal islands having a surrounding N.sup.+ periphery and an N.sup.