Patents by Inventor Paul William Wells

Paul William Wells has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12095651
    Abstract: In one embodiment, an apparatus includes one or more processors and one or more computer-readable non-transitory storage media coupled to the one or more processors. The one or more computer-readable non-transitory storage media include instructions that, when executed by the one or more processors, cause the apparatus to perform operations including receiving a first type-length-value (TLV) associated with a winning flexible algorithm definition (FAD) from a first element of a network. The operations also include determining a security level for the winning FAD based on the TLV. The operations further include determining a data transmission route through a plurality of elements of the network based on the security level for the winning FAD.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: September 17, 2024
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Peter Psenak, Paul William Wells, Ketan Jivan Talaulikar, Clarence Filsfils
  • Publication number: 20210377152
    Abstract: In one embodiment, an apparatus includes one or more processors and one or more computer-readable non-transitory storage media coupled to the one or more processors. The one or more computer-readable non-transitory storage media include instructions that, when executed by the one or more processors, cause the apparatus to perform operations including receiving a first type-length-value (TLV) associated with a winning flexible algorithm definition (FAD) from a first element of a network. The operations also include determining a security level for the winning FAD based on the TLV. The operations further include determining a data transmission route through a plurality of elements of the network based on the security level for the winning FAD.
    Type: Application
    Filed: August 11, 2021
    Publication date: December 2, 2021
    Inventors: Peter Psenak, Paul William Wells, Ketan Jivan Talaulikar, Clarence Filsfils
  • Patent number: 11121961
    Abstract: In one embodiment, an apparatus includes one or more processors and one or more computer-readable non-transitory storage media coupled to the one or more processors. The one or more computer-readable non-transitory storage media include instructions that, when executed by the one or more processors, cause the apparatus to perform operations including receiving a first type-length-value (TLV) associated with a winning flexible algorithm definition (FAD) from a first element of a network. The operations also include determining a security level for the winning FAD based on the TLV. The operations further include determining a data transmission route through a plurality of elements of the network based on the security level for the winning FAD.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: September 14, 2021
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Peter Psenak, Paul William Wells, Ketan Jivan Talaulikar, Clarence Filsfils
  • Publication number: 20210225192
    Abstract: A method, system and associate peripheral device for remotely teaching piano. The device (13/23) comprises a plurality of indicator LEDs along its length for arrangement/alignment across a student piano keyboard (11). When a key is triggered on a remote piano keyboard (21), e.g., by a teacher, one of the LEDs lights up at the equivalent key at the student piano keyboard. The system also allows for playing notes from the student or teacher piano keyboard, communicated over the internet, at the teacher or student piano keyboard and vice versa.
    Type: Application
    Filed: February 5, 2021
    Publication date: July 22, 2021
    Inventor: Paul William WELLS
  • Publication number: 20200322254
    Abstract: In one embodiment, an apparatus includes one or more processors and one or more computer-readable non-transitory storage media coupled to the one or more processors. The one or more computer-readable non-transitory storage media include instructions that, when executed by the one or more processors, cause the apparatus to perform operations including receiving a first type-length-value (TLV) associated with a winning flexible algorithm definition (FAD) from a first element of a network. The operations also include determining a security level for the winning FAD based on the TLV. The operations further include determining a data transmission route through a plurality of elements of the network based on the security level for the winning FAD.
    Type: Application
    Filed: October 10, 2019
    Publication date: October 8, 2020
    Inventors: Peter Psenak, Paul William Wells, Ketan Jivan Talaulikar, Clarence Filsfils
  • Publication number: 20120166675
    Abstract: In one embodiment, a link state advertisement is generated. A first value and a second value are read from the link state advertisement. The first value and the second value are combined to create a combined value. The combined value is input to a hash algorithm that performs a hash function on the combined value to produce a resulting value. The resulting value is used as a link state identifier of the link state advertisement.
    Type: Application
    Filed: March 7, 2012
    Publication date: June 28, 2012
    Applicant: CISCO TECHNOLOGY, INC.
    Inventor: Paul William Wells
  • Patent number: 8161185
    Abstract: In one embodiment, a technique is used by a routing system to generate a link state identifier for a link state advertisement message. The routing system generates the link state advertisement message. A prefix length is read from the link state advertisement message. Further, a prefix is read from the link state advertisement message. A hash function is performed on the prefix and the length to produce a result by appending the length to the prefix to generate a combined value, inputting the combined value to a hash algorithm, and using at least a portion of an output of the hash algorithm as the result. The link state identifier is determined from the result of the hash function.
    Type: Grant
    Filed: April 24, 2006
    Date of Patent: April 17, 2012
    Assignee: Cisco Technology, Inc.
    Inventor: Paul William Wells
  • Patent number: D952026
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: May 17, 2022
    Inventor: Paul William Wells