Abstract: In example embodiments, methods are provided for reducing bit line leakage current. In an example embodiment, an unselected program word line is biased to a bias voltage. The unselected program word line is connected to a memory cell and the memory cell includes a plurality of transistors. In another example embodiment, an unselected memory cell is biased to a negative bias voltage during read operations.

Abstract: In example embodiments, methods are provided for reducing bit line leakage current. In an example embodiment, an unselected program word line is biased to a bias voltage. The unselected program word line is connected to a memory cell and the memory cell includes a plurality of transistors. In another example embodiment, an unselected memory cell is biased to a negative bias voltage during read operations.

Abstract: An integrated circuit memory device has a plurality of memory cells arranged in a plurality of arrays. Each array has a plurality of rows, and a plurality of column lines, and a plurality of row lines connecting to the memory cells in each array. The memory cell in an array is addressable by a column line and a row line. A column address decoder receives a column address signal and selects one or more column lines of each array in response. A row address decoder receives a row address signal and selects a row line of each array in response. The memory device also has a plurality (k) of sense amplifiers, with one sense amplifier associated with each array, connectable to one or more column lines of the array and receives a signal therefrom supplied from an addressed memory cell. The memory device further has a register; and a control circuit.

Abstract: An integrated circuit memory device has an array of memory cells arranged in a plurality of rows and columns and a plurality of row lines and a plurality of column lines. Cells arranged in the same row are connected by a common row line, and cells arranged in the same column are connected by a common column line. Each cell in the array is addressed by an address signal which has a plurality of bits. A sense amplifier circuit is connectable to one or more of the plurality of column lines of the array. An address input terminal receives in series the plurality of bits of the address signal. Each of the column lines is connectable to a pre-charge voltage, in response to a read command.

Abstract: A method for programming an integrated memory circuit and an integrated memory circuit structure for storing information are disclosed. The method of programming includes the steps of providing a program mode for programming the memory cells in accordance with total number of memory cells that is required to be programmed; and programming the memory cells in accordance with the program mode. The integrated memory circuit includes a program mode determining circuit, and a programming circuit operatively coupled to the program mode determining circuit for programming each of a plurality of block of memory cells according to its respective program mode.

Abstract: An E.sup.2 PROM is disclosed which provides automatic programming verification. Before data is written into the cells, the cells are automatically erased. The contents of the cells are checked to verify that erasing has been completed. If it has not, erasing is continued until the cells are erased. When data is written into the cells, the writing of the data into the cells continues until programming is verified. The verification is conducted at potentials other than the normal reference potential to assure that the cells are well programmed with either binary zeroes or binary ones.