Patents by Inventor Pei-Haw Tsao

Pei-Haw Tsao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200035615
    Abstract: A non-conductive magnetic shield material is provided for use in magnetic shields of semiconductor packaging. The material is made magnetic by the incorporation of ferromagnetic particles into a polymer matrix, and is made non-conductive by the provision of an insulating coating on the ferromagnetic particles.
    Type: Application
    Filed: May 7, 2019
    Publication date: January 30, 2020
    Inventors: Tsung-Hsing LU, Pei-Haw TSAO, Li-Huan CHU
  • Publication number: 20200020603
    Abstract: Generally, the present disclosure provides example embodiments relating to a package attached to a printed circuit board (PCB). In an embodiment, a structure includes a PCB. The PCB has ball pads arranged in a matrix. Outer ball pads are along one or more outer edges of the matrix, and each of the outer ball pads has a first solder-attach area. Inner ball pads are interior to the matrix, and each of the inner ball pads has a second solder-attach area. The first solder-attach area is larger than the second solder-attach area.
    Type: Application
    Filed: July 16, 2018
    Publication date: January 16, 2020
    Inventors: Pei-Haw TSAO, Tsung-Hsing LU, Li-Huan CHU
  • Publication number: 20200006098
    Abstract: The current disclosure describes carrier tape systems that include a carrier tape substrate and a cover tape. The carrier tape system includes a plurality of repetitive adhesion areas where the carrier tape substrate and cover tape are attached to each other and non-adhesion areas where the carrier tape substrate and cover tape are not attached to each other. Separating the cover tape and the carrier tape substrate at these repetitive adhesion and non-adhesion areas imparts a vibration to the cover tape which impedes or prevents semiconductor devices carried in pockets of the carrier tape substrate from adhering to adhesive on the cover tape.
    Type: Application
    Filed: March 28, 2019
    Publication date: January 2, 2020
    Inventors: Tsung-Jen LIAO, Pei-Haw TSAO, Tsui-Mei CHEN
  • Publication number: 20200008330
    Abstract: The current disclosure describes a carrier tape systems, which include a cover tape having adhesion areas and non-adhesion areas which are substantially free of adhesive. Methods for supplying semiconductor devices to an apparatus, which in operation, places the semiconductor devices at desired locations are also described. Methods of forming a semiconductor device carrier system are also described.
    Type: Application
    Filed: March 4, 2019
    Publication date: January 2, 2020
    Inventors: Sung-Sheng CHIU, Pei-Haw TSAO, Tsui-Mei CHEN, Shih-Hsing LIN, Li-Huan CHU
  • Patent number: 10510633
    Abstract: Generally, the present disclosure provides example embodiments relating to a package that may be attached to a printed circuit board (PCB). In an embodiment, a structure includes a package. The package includes one or more dies and metal pads on an exterior surface of the package. At least some of the metal pads are first solder ball pads. The structure further includes pins, and each of the pins is attached to a respective one of the metal pads.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pei-Haw Tsao, Tsung-Hsing Lu, Li-Huan Chu
  • Patent number: 10506712
    Abstract: Generally, the present disclosure provides example embodiments relating to a printed circuit board (PCB). In an embodiment, a structure includes a PCB including insulating layers with respective metal layers being disposed therebetween. Each of first layers of the insulating layers includes a first fiberglass content. A second layer of the insulating layers has a second fiberglass content less than the first fiberglass content. For example, in some embodiments, the second insulating layer does not include a fiberglass matrix.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: December 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Haw Tsao, Tsung-Hsing Lu, Li-Huan Chu
  • Patent number: 10475719
    Abstract: A semiconductor structure includes a substrate comprising a die pad disposed over the substrate, and a passivation disposed over the substrate and surrounding the die pad, a redistribution layer (RDL) comprising a dielectric layer disposed over the passivation and an interconnect structure disposed within the dielectric layer and electrically connecting with the die pad, a conductive bump disposed over and electrically connected with the interconnect structure; and an isolation layer surrounding the substrate and the RDL.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: November 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Pei-Haw Tsao, Chien-Jung Wang
  • Patent number: 10373901
    Abstract: A semiconductor structure includes a first substrate including a first surface and a second surface opposite to the first surface; a second substrate including a third surface and a fourth surface opposite to the third surface; a polymeric layer disposed between the second surface of the first substrate and the third surface of the second substrate; a first conductive via extended through the first substrate, the second substrate and the polymeric layer; a second conductive via extended through the first substrate, the second substrate and the polymeric layer; and a third conductive via extended through the first substrate, the second substrate and the polymeric layer, wherein the second conductive via is disposed between the first conductive via and the third conductive via, the second conductive via is configured to connect to a signal source, the first conductive via and the third conductive via are configured to connect to electrical ground.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: August 6, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Pei-Haw Tsao, Tsung-Hsing Lu, Li-Huan Chu
  • Publication number: 20190164920
    Abstract: A semiconductor device includes a substrate and at least one bump structure disposed over the substrate. The at least one bump structure includes a pillar formed of a metal having a lower solderability than copper or a copper alloy to a solder alloy disposed over the substrate. A solder alloy is formed directly over and in contact with an upper surface of the metal having the lower solderability than copper or a copper alloy. The pillar has a height of greater than 10 ?m.
    Type: Application
    Filed: October 24, 2018
    Publication date: May 30, 2019
    Inventors: Pei-Haw TSAO, Chen-Shien CHEN, Cheng-Hung TSAI, Kuo-Chin CHANG, Li-Huan CHU
  • Patent number: 10304793
    Abstract: Package structures and methods for forming the package structures are provided. A package structure includes a molding compound having a surface. The package structure also includes an integrated circuit die in the molding compound. The integrated circuit die has a portion protruding from the surface. The package structure further includes a planarization layer covering the surface. The planarization layer surrounds the portion of the integrated circuit die. In addition, the package structure includes a redistribution layer electrically connected to the integrated circuit die. The redistribution layer covers the planarization layer and the integrated circuit die.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: May 28, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Hsing Lu, Pei-Haw Tsao
  • Publication number: 20190148317
    Abstract: A package structure is provided. The package structure includes a first under bump metallurgy (UBM) layer formed over a first substrate, a first protrusion structure formed over the first UBM layer, wherein the first protrusion structure extends upward away from the first UBM layer. The package structure includes a first electrical connector formed over the first protrusion structure. The first electrical connector is surrounded by the first protrusion structure, and the first protrusion structure has an outer sidewall surface, and the outer sidewall surface of the first protrusion structure is aligned with an outer surface of the first UBM layer.
    Type: Application
    Filed: December 19, 2018
    Publication date: May 16, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Haw TSAO, Chen-Shien CHEN, Li-Huan CHU
  • Patent number: 10283424
    Abstract: Packaging method and wafer structures are described. A semiconductor wafer having dies, scribe streets surrounding the dies and between the dies and test pads in the scribe streets is provided. Wafer testing is performed to the semiconductor wafer through the test pads. A laser grooving process is performed to the semiconductor wafer along the scribe streets and the test pads in the scribe streets are removed to form laser scanned regions in the scribe streets. A mechanical dicing process is performed cutting through the semiconductor wafer along the scribe streets to singulate the dies. The singulated dies are packaged.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: May 7, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsui-Mei Chen, Pei-Haw Tsao, Cheng-Te Lin, Yu-Jung Lin, Li-Huan Chu
  • Publication number: 20190096832
    Abstract: A method for fabricating a semiconductor structure is provided. The method includes: providing a semiconductor chip comprising an active surface; forming a conductive bump over the active surface of the semiconductor chip; and coupling the conductive bump to a substrate. The conductive bump includes a plurality of bump segments including a first group of bump segments and a second group of bump segments. Each bump segment has a same segment thickness in a direction orthogonal to the active surface of the semiconductor chip, and each bump segment has a volume defined by a multiplication of the same segment thickness with an average cross-sectional area of the bump segment in a plane parallel to the active surface of the semiconductor chip. A ratio of a total volume of the first group of bump segments to a total volume of the second group of bump segments is between 0.03 and 0.8.
    Type: Application
    Filed: November 30, 2018
    Publication date: March 28, 2019
    Inventors: PEI-HAW TSAO, AN-TAI XU, HUANG-TING HSIAO, KUO-CHIN CHANG
  • Patent number: 10163827
    Abstract: A package structure is provided. The package structure includes a dielectric layer formed over a first substrate and a conductive layer formed in the dielectric layer. The package structure includes an under bump metallurgy (UBM) layer formed over the dielectric layer, and the UBM layer is electrically connected to the conductive layer. The package structure also includes a first protrusion structure formed over the UBM layer, and the first protrusion structure extends upward away from the UBM layer. The package structure further includes a second protrusion structure formed over the UBM layer, and the second protrusion structure extends upward away from the UBM layer. The package structure includes a first conductive connector formed over the first protrusion structure; and a second conductive connector formed over the second protrusion structure. An air gap is formed between the first protrusion structure and the second protrusion structure.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pei-Haw Tsao, Chen-Shien Chen, Li-Huan Chu
  • Publication number: 20180308779
    Abstract: A semiconductor structure includes a substrate comprising a die pad disposed over the substrate, and a passivation disposed over the substrate and surrounding the die pad, a redistribution layer (RDL) comprising a dielectric layer disposed over the passivation and an interconnect structure disposed within the dielectric layer and electrically connecting with the die pad, a conductive bump disposed over and electrically connected with the interconnect structure; and an isolation layer surrounding the substrate and the RDL.
    Type: Application
    Filed: June 29, 2018
    Publication date: October 25, 2018
    Inventors: PEI-HAW TSAO, CHIEN-JUNG WANG
  • Patent number: 10020239
    Abstract: A semiconductor structure includes a substrate comprising a die pad disposed over the substrate, and a passivation disposed over the substrate and surrounding the die pad, a redistribution layer (RDL) comprising a dielectric layer disposed over the passivation and an interconnect structure disposed within the dielectric layer and electrically connecting with the die pad, a conductive bump disposed over and electrically connected with the interconnect structure; and an isolation layer surrounding the substrate and the RDL.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: July 10, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Pei-Haw Tsao, Chien-Jung Wang
  • Publication number: 20180151498
    Abstract: Package structures and methods for forming the package structures are provided. A package structure includes a molding compound having a surface. The package structure also includes an integrated circuit die in the molding compound. The integrated circuit die has a portion protruding from the surface. The package structure further includes a planarization layer covering the surface. The planarization layer surrounds the portion of the integrated circuit die. In addition, the package structure includes a redistribution layer electrically connected to the integrated circuit die. The redistribution layer covers the planarization layer and the integrated circuit die.
    Type: Application
    Filed: November 29, 2016
    Publication date: May 31, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Hsing LU, Pei-Haw TSAO
  • Patent number: 9880220
    Abstract: According to an exemplary embodiment, a method of detecting edge cracks in a die under test is provided. The method includes the following operations: receiving a command signal; providing power from the command signal; providing a response signal based on the command signal; and self-destructing based on the command signal.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: January 30, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Huang-Ting Hsiao, An-Tai Xu, Pei-Haw Tsao, Cheng-Hung Tsai, Tsui-Mei Chen, Nai-Cheng Lu
  • Patent number: 9859235
    Abstract: A system and method for forming an underbump metallization (UBM) is presented. A preferred embodiment includes a raised UBM which extends through a passivation layer so as to make contact with a contact pad while retaining enough of the passivation layer between the contact pad and the UBM to adequately handle the peeling and shear stress that results from CTE mismatch and subsequent thermal processing. The UBM contact is preferably formed in either an octagonal ring shape or an array of contacts.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: January 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Wen Liu, Hao-Yi Tsai, Hsien-Wei Chen, Shin-Puu Jeng, Ying-Ju Chen, Shang-Yun Hou, Pei-Haw Tsao, Chen-Hua Yu
  • Patent number: 9780046
    Abstract: An embodiment device includes a semiconductor substrate and an interconnect structure over the semiconductor substrate. The interconnect structure includes a functional circuit region and a first portion of a seal ring spaced apart from the functional circuit region by a buffer zone. The device also includes a passivation layer over the interconnect structure and a second portion of the seal ring over the passivation layer and connected the first portion of the seal ring. The second portion of the seal ring is disposed in the buffer zone.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: October 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Yu Pan, Han-Ping Pu, Pei-Haw Tsao, Yu-Chen Hsu