Patents by Inventor Pei-Haw Tsao

Pei-Haw Tsao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12205859
    Abstract: Generally, the present disclosure provides example embodiments relating to a package that may be attached to a printed circuit board (PCB). In an embodiment, a structure includes a package. The package includes one or more dies and metal pads on an exterior surface of the package. At least some of the metal pads are first solder ball pads. The structure further includes pins, and each of the pins is attached to a respective one of the metal pads.
    Type: Grant
    Filed: March 20, 2023
    Date of Patent: January 21, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Haw Tsao, Tsung-Hsing Lu, Li-Huan Chu
  • Patent number: 12159847
    Abstract: An integrated fan-out structure on a semiconductor die, method of making the same and method of testing the semiconductor die are disclosed. The semiconductor die includes a bond pad and a hole formed in the bond pad, a passivation layer formed over a portion of the bond pad, and a protective layer formed over the hole in the bond pad.
    Type: Grant
    Filed: July 19, 2022
    Date of Patent: December 3, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tsui-Mei Chen, Tsung-Jen Liao, Li-Huan Chu, Pei-Haw Tsao
  • Publication number: 20240395621
    Abstract: A method includes receiving a first wafer having a first device layer on a first semiconductor substrate, receiving a second wafer having a second device layer on a second semiconductor substrate, forming a first groove along a first scribing channel of the first wafer with a non-mechanical cutting process, and forming a second groove along a second scribing channel of the second wafer with the non-mechanical cutting process. The method further includes after the forming of the first and second grooves, bonding the first and second wafers together, and dicing the bonded first and second wafers through the first and second grooves with a mechanical cutting process.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 28, 2024
    Inventors: Tsung-Hsing Lu, Jun He, Li-Huan Chu, Pei-Haw Tsao
  • Publication number: 20240379640
    Abstract: A method of forming a semiconductor device package is provided, including bonding passive devices to a first surface of a package substrate; forming a first underfill element on the first surface to surround the passive devices; forming a first molding layer to encapsulate the passive devices and the first underfill element; bonding a die to a second surface of the package substrate; forming a second underfill element on the second surface to surround the die; forming a second molding layer to encapsulate the die and the second underfill element; forming openings in the second molding layer to expose contact pads formed on the second surface of the package substrate; and disposing conductive bumps in the openings to electrically contact the contact pads, wherein the conductive bumps is in direct contact with the second surface and exposed from the second molding layer.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Heh-Chang HUANG, Fu-Jen LI, Pei-Haw TSAO, Shyue-Ter LEU
  • Publication number: 20240347479
    Abstract: A semiconductor package includes a package substrate having a top surface and an opposing bottom surface. The package substrate includes a top build-up wiring layer and an upper dielectric layer covering the top build-up wiring layer. A semiconductor device and a passive component are mounted on the top surface of the package substrate in a side-by-side manner. A molding compound encapsulates the semiconductor device and the passive component on the top surface of the package substrate. A cavity is disposed between the passive component and the top surface of the package substrate.
    Type: Application
    Filed: March 20, 2024
    Publication date: October 17, 2024
    Applicant: MEDIATEK INC.
    Inventors: Chu-Chia Chang, Pei-Haw Tsao, Peng-Yu Huang, Yu-Liang Hsiao, Wei-Fan Chen
  • Publication number: 20240290737
    Abstract: A bump structure includes a conductive pad on a semiconductor die; a passivation layer covering a perimeter of the conductive pad; and a first polymer layer on the passivation layer. The first polymer layer includes a via opening partially exposing the central portion of the conductive pad. A RDL is disposed on the first polymer layer and patterned into a bump pad situated directly above the conductive pad. The via opening is completely filled with the RDL and a RDL via is integrally formed with the bump pad. A second polymer layer is disposed on the first polymer layer. An island of the second polymer layer is disposed at a central portion of the bump pad. UBM layer is disposed on the bump pad. The UBM layer covers the island and forms a bulge thereon. A bump is disposed on the UBM layer.
    Type: Application
    Filed: January 21, 2024
    Publication date: August 29, 2024
    Applicant: MEDIATEK INC.
    Inventors: Hung-Pin Tsai, Pei-Haw Tsao, Nai-Wei Liu, Wen-Sung Hsu
  • Patent number: 12051624
    Abstract: A semiconductor structure includes a first device and a second device bonded on the first device. The first device has a first sidewall distal to the second device and a second sidewall proximal to the second device. A surface roughness of the second sidewall is larger than a surface roughness of the first sidewall.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: July 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Hsing Lu, Jun He, Li-Huan Chu, Pei-Haw Tsao
  • Publication number: 20240243098
    Abstract: A semiconductor package includes a package substrate, an interposer on and electrically connected to the package substrate, a central logic die disposed on and electrically connected to the interposer, peripheral function dies disposed on and electrically connected to the interposer and located in proximity to the central logic die, and at least one dummy die disposed between the central logic die and the peripheral function dies so as to form a rectangular shaped die arrangement. The at least one dummy die is disposed at a corner position of the rectangular shaped die arrangement.
    Type: Application
    Filed: December 17, 2023
    Publication date: July 18, 2024
    Applicant: MEDIATEK INC.
    Inventors: Pei-Haw Tsao, Te-Chi Wong
  • Patent number: 12016126
    Abstract: The current disclosure describes carrier tape systems, which include a cover tape having adhesion areas and non-adhesion areas which are substantially free of adhesive. Methods for supplying semiconductor devices to an apparatus, which in operation, places the semiconductor devices at desired locations are also described. Methods of forming a semiconductor device carrier system are also described.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: June 18, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sung-Sheng Chiu, Pei-Haw Tsao, Tsui-Mei Chen, Shih-Hsing Lin, Li-Huan Chu
  • Publication number: 20240178173
    Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes an interconnect layer over the substrate. The chip structure includes a conductive pad over the interconnect layer. The chip structure includes a conductive bump over the conductive pad. The conductive bump has a first portion, a second portion, and a neck portion between the first portion and the second portion, the first portion is between the neck portion and the conductive pad, and the neck portion is narrower than both of the first portion and the second portion. The chip structure includes a support layer over the second portion of the conductive bump. A first composition of the support layer is different from a second composition of the conductive bump. The chip structure includes a solder structure over the support layer.
    Type: Application
    Filed: February 1, 2024
    Publication date: May 30, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Cheng CHEN, Pei-Haw TSAO
  • Publication number: 20240178159
    Abstract: A coreless substrate package includes a coreless substrate; a package device mounted on a coreless substrate; an underfill material filling into a space between the package device and the coreless substrate; a stiffener ring disposed on a top surface of the coreless substrate along perimeter of the coreless substrate; and a gap fill material disposed in a gap between the stiffener ring and the package device.
    Type: Application
    Filed: November 6, 2023
    Publication date: May 30, 2024
    Applicant: MEDIATEK INC.
    Inventors: Pei-Haw Tsao, Te-Chi Wong
  • Publication number: 20240178112
    Abstract: A semiconductor package structure includes a semiconductor substrate, a conductive pad on the semiconductor substrate, and a passivation layer on the semiconductor substrate and the conductive pad. The passivation layer exposes a portion of the top surface of the conductive pad. The semiconductor package structure also includes a conductive adhesive layer on the conductive pad, and a dielectric layer on the passivation layer and the conductive adhesive layer. The dielectric layer exposes a portion of the conductive adhesive layer. The semiconductor package structure also includes a redistribution layer (RDL) structure on the dielectric layer and electrically connected to the conductive pad through the conductive adhesive layer. The semiconductor package structure also includes a bump structure over the RDL structure.
    Type: Application
    Filed: November 9, 2023
    Publication date: May 30, 2024
    Inventors: Yu-Tung CHEN, Kuo-Lung FAN, Yen-Yao CHI, Nai-Wei LIU, Pei-Haw TSAO
  • Patent number: 11990423
    Abstract: A non-conductive magnetic shield material is provided for use in magnetic shields of semiconductor packaging. The material is made magnetic by the incorporation of ferromagnetic particles into a polymer matrix, and is made non-conductive by the provision of an insulating coating on the ferromagnetic particles.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: May 21, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Hsing Lu, Pei-Haw Tsao, Li-Huan Chu
  • Patent number: 11978729
    Abstract: A semiconductor device package and a method of forming the same are provided. The semiconductor device package includes a package substrate having a first surface and a second surface opposite to the first surface. Several integrated devices are bonded to the first surface of the package substrate. A first underfill element is disposed over the first surface and surrounds the integrated devices. A first molding layer is disposed over the first surface and surrounds the integrated devices and the first underfill element. A semiconductor die is bonded to the second surface of the package substrate. A second underfill element is disposed over the second surface and surrounds the semiconductor die. A second molding layer is disposed over the second surface and surrounds the semiconductor die and the second underfill element. Several conductive bumps are disposed over the second surface and adjacent to the second molding layer.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Heh-Chang Huang, Fu-Jen Li, Pei-Haw Tsao, Shyue-Ter Leu
  • Publication number: 20240145448
    Abstract: A semiconductor device package and a method of forming the same are provided. The semiconductor device package includes a package substrate having a first surface and a second surface opposite to the first surface. Several integrated devices are bonded to the first surface of the package substrate. A first underfill element is disposed over the first surface and surrounds the integrated devices. A first molding layer is disposed over the first surface and surrounds the integrated devices and the first underfill element. A semiconductor die is bonded to the second surface of the package substrate. A second underfill element is disposed over the second surface and surrounds the semiconductor die. A second molding layer is disposed over the second surface and surrounds the semiconductor die and the second underfill element. Several conductive bumps are disposed over the second surface and adjacent to the second molding layer.
    Type: Application
    Filed: January 9, 2024
    Publication date: May 2, 2024
    Inventors: Heh-Chang HUANG, Fu-Jen LI, Pei-Haw TSAO, Shyue-Ter LEU
  • Publication number: 20240112963
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor wafer and a test structure. The semiconductor wafer has a substrate having a scribe line area, a first die area and a second die area. The first die area and the second die area are separated by the scribe line area extending along a first direction. The test structure is disposed in the scribe line area. The test structure includes a test device and a first test pad. The test device has a physical characteristic similar to a semiconductor device fabricated in the first die area or the second die area. The first test pad is electrically connected to the test device. A first distance between the first test pad and the first die area gradually increases from a center region to a peripheral region of the first test pad in the first direction.
    Type: Application
    Filed: August 8, 2023
    Publication date: April 4, 2024
    Inventors: Yu-Tung CHEN, Pei-Haw TSAO, Kuo-Lung FAN, Yuan-Fu CHUNG
  • Patent number: 11894331
    Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes an interconnect layer over the substrate. The chip structure includes a conductive pad over the interconnect layer. The chip structure includes a conductive bump over the conductive pad. The conductive bump has a first portion, a second portion, and a neck portion between the first portion and the second portion. The first portion is between the neck portion and the conductive pad. The neck portion is narrower than the first portion and narrower than the second portion.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: February 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Cheng Chen, Pei-Haw Tsao
  • Publication number: 20230402324
    Abstract: A semiconductor structure includes a first device and a second device bonded on the first device. The first device has a first sidewall distal to the second device and a second sidewall proximal to the second device. A surface roughness of the second sidewall is larger than a surface roughness of the first sidewall. The second device has a third sidewall proximal to the first device and a fourth sidewall distal to the first device. A surface roughness of the fourth sidewall is larger than a surface roughness of the third sidewall.
    Type: Application
    Filed: August 10, 2023
    Publication date: December 14, 2023
    Inventors: Tsung-Hsing Lu, Jun He, Li-Huan Chu, Pei-Haw Tsao
  • Publication number: 20230387101
    Abstract: In an embodiment, a method of forming an integrated circuit package includes: attaching a first carrier to a package component, the package component comprising: an interposer; a first semiconductor die attached to a first side of the interposer; a second semiconductor die attached to the first side of the interposer; an encapsulant encapsulating the first semiconductor die and the second semiconductor die; and conductive connectors attached to a second side of the interposer; attaching a second carrier to a package substrate, the package substrate comprising bond pads; bonding the conductive connectors of the package component to the bond pads of the package substrate by reflowing the conductive connectors while the first carrier is attached to the package component and while the second carrier is attached to the package substrate; removing the first carrier; and removing the second carrier.
    Type: Application
    Filed: May 31, 2022
    Publication date: November 30, 2023
    Inventors: Pei-Haw Tsao, Chien-Li Kuo, Kuo-Chio Liu
  • Publication number: 20230386954
    Abstract: A wafer level chip scale package includes a bare silicon die having an active surface, a rear surface opposite to the active surface, and a sidewall surface between the active surface and the rear surface. The bare silicon die includes a backside corner between the rear surface and the sidewall surface. A plurality of pads is disposed on the active surface. A plurality of conductive elements is disposed on the plurality of pads, respectively. A backside tape is adhered to the rear surface by using an adhesive layer. The adhesive layer and the backside tape protrude beyond the sidewall surfaces of the bare silicon die. The adhesive layer extends along the sidewall surface and wraps around the backside corner.
    Type: Application
    Filed: April 10, 2023
    Publication date: November 30, 2023
    Applicant: MEDIATEK INC.
    Inventors: Yu-Tung Chen, Pei-Haw Tsao, Kuo-Lung Fan