Patents by Inventor Pei-Haw Tsao

Pei-Haw Tsao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220336370
    Abstract: A non-conductive magnetic shield material is provided for use in magnetic shields of semiconductor packaging. The material is made magnetic by the incorporation of ferromagnetic particles into a polymer matrix, and is made non-conductive by the provision of an insulating coating on the ferromagnetic particles.
    Type: Application
    Filed: June 28, 2022
    Publication date: October 20, 2022
    Inventors: Tsung-Hsing LU, Pei-Haw TSAO, Li-Huan CHU
  • Patent number: 11404383
    Abstract: A non-conductive magnetic shield material is provided for use in magnetic shields of semiconductor packaging. The material is made magnetic by the incorporation of ferromagnetic particles into a polymer matrix, and is made non-conductive by the provision of an insulating coating on the ferromagnetic particles.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Hsing Lu, Pei-Haw Tsao, Li-Huan Chu
  • Publication number: 20220110232
    Abstract: The current disclosure describes carrier tape systems, which include a cover tape having adhesion areas and non-adhesion areas which are substantially free of adhesive. Methods for supplying semiconductor devices to an apparatus, which in operation, places the semiconductor devices at desired locations are also described. Methods of forming a semiconductor device carrier system are also described.
    Type: Application
    Filed: December 17, 2021
    Publication date: April 7, 2022
    Inventors: Sung-Sheng CHIU, Pei-Haw TSAO, Tsui-Mei CHEN, Shih-Hsing LIN, Li-Huan CHU
  • Patent number: 11239143
    Abstract: A semiconductor structure includes a first substrate including a first surface and a second surface opposite to the first surface; a first conductive via extended through the first substrate; a second conductive via extended through the first substrate; and a third conductive via extended through the first substrate, wherein the second conductive via is disposed between the first conductive via and the third conductive via, the second conductive via is configured to connect to a signal source, and the first conductive via and the third conductive via are configured to connect to an electrical ground.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: February 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Pei-Haw Tsao, Tsung-Hsing Lu, Li-Huan Chu
  • Patent number: 11240947
    Abstract: The current disclosure describes carrier tape systems, which include a cover tape having adhesion areas and non-adhesion areas which are substantially free of adhesive. Methods for supplying semiconductor devices to an apparatus, which in operation, places the semiconductor devices at desired locations are also described. Methods of forming a semiconductor device carrier system are also described.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: February 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sung-Sheng Chiu, Pei-Haw Tsao, Tsui-Mei Chen, Shih-Hsing Lin, Li-Huan Chu
  • Publication number: 20210358808
    Abstract: A semiconductor structure includes a first device and a second device bonded on the first device. The first device has a first sidewall distal to the second device and a second sidewall proximal to the second device. A surface roughness of the second sidewall is larger than a surface roughness of the first sidewall.
    Type: Application
    Filed: July 28, 2021
    Publication date: November 18, 2021
    Inventors: Tsung-Hsing Lu, Jun He, Li-Huan Chu, Pei-Haw Tsao
  • Publication number: 20210343667
    Abstract: An integrated fan-out structure on a semiconductor die, method of making the same and method of testing the semiconductor die are disclosed. The semiconductor die includes a bond pad and a hole formed in the bond pad, a passivation layer formed over a portion of the bond pad, and a protective layer formed over the hole in the bond pad.
    Type: Application
    Filed: February 4, 2021
    Publication date: November 4, 2021
    Inventors: Tsui-Mei CHEN, Tsung-Jen LIAO, Li-Huan CHU, Pei-Haw TSAO
  • Patent number: 11164764
    Abstract: The current disclosure describes carrier tape systems that include a carrier tape substrate and a cover tape. The carrier tape system includes a plurality of repetitive adhesion areas where the carrier tape substrate and cover tape are attached to each other and non-adhesion areas where the carrier tape substrate and cover tape are not attached to each other. Separating the cover tape and the carrier tape substrate at these repetitive adhesion and non-adhesion areas imparts a vibration to the cover tape which impedes or prevents semiconductor devices carried in pockets of the carrier tape substrate from adhering to adhesive on the cover tape.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: November 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Jen Liao, Pei-Haw Tsao, Tsui-Mei Chen
  • Patent number: 11164763
    Abstract: The current disclosure describes carrier tape systems that include a carrier tape substrate and a cover tape. The carrier tape system includes a plurality of repetitive adhesion areas where the carrier tape substrate and cover tape are attached to each other and non-adhesion areas where the carrier tape substrate and cover tape are not attached to each other. Separating the cover tape and the carrier tape substrate at these repetitive adhesion and non-adhesion areas imparts a vibration to the cover tape which impedes or prevents semiconductor devices carried in pockets of the carrier tape substrate from adhering to adhesive on the cover tape.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: November 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Jen Liao, Pei-Haw Tsao, Tsui-Mei Chen
  • Publication number: 20210305116
    Abstract: A semiconductor structure includes a substrate comprising a die pad disposed over the substrate, and a passivation disposed over the substrate and surrounding the die pad, a redistribution layer (RDL) comprising a dielectric layer disposed over the passivation and an interconnect structure disposed within the dielectric layer and electrically connecting with the die pad, a conductive bump disposed over and electrically connected with the interconnect structure; and an isolation layer surrounding the substrate and the RDL.
    Type: Application
    Filed: June 10, 2021
    Publication date: September 30, 2021
    Inventors: PEI-HAW TSAO, CHIEN-JUNG WANG
  • Patent number: 11127704
    Abstract: A semiconductor device includes a substrate and at least one bump structure disposed over the substrate. The at least one bump structure includes a pillar formed of a metal having a lower solderability than copper or a copper alloy to a solder alloy disposed over the substrate. A solder alloy is formed directly over and in contact with an upper surface of the metal having the lower solderability than copper or a copper alloy. The pillar has a height of greater than 10 ?m.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: September 21, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Haw Tsao, Chen-Shien Chen, Cheng-Hung Tsai, Kuo-Chin Chang, Li-Huan Chu
  • Patent number: 11101190
    Abstract: Generally, the present disclosure provides example embodiments relating to a package attached to a printed circuit board (PCB). In an embodiment, a structure includes a PCB. The PCB has ball pads arranged in a matrix. Outer ball pads are along one or more outer edges of the matrix, and each of the outer ball pads has a first solder-attach area. Inner ball pads are interior to the matrix, and each of the inner ball pads has a second solder-attach area. The first solder-attach area is larger than the second solder-attach area.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: August 24, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pei-Haw Tsao, Tsung-Hsing Lu, Li-Huan Chu
  • Patent number: 11081392
    Abstract: A method includes providing first and second wafers; forming a first device layer in a top portion of the first wafer; forming a second device layer in a top portion of the second wafer; forming a first groove in the first device layer; forming a second groove in the second device layer; bonding the first and second wafers together after at least one of the first and second grooves is formed; and dicing the bonded first and second wafers by a cutting process, wherein the cutting process cuts through the first and second grooves.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: August 3, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Hsing Lu, Jun He, Li-Huan Chu, Pei-Haw Tsao
  • Patent number: 11037849
    Abstract: A semiconductor structure includes a substrate comprising a die pad disposed over the substrate, and a passivation disposed over the substrate and surrounding the die pad, a redistribution layer (RDL) comprising a dielectric layer disposed over the passivation and an interconnect structure disposed within the dielectric layer and electrically connecting with the die pad, a conductive bump disposed over and electrically connected with the interconnect structure; and an isolation layer surrounding the substrate and the RDL.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: June 15, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Pei-Haw Tsao, Chien-Jung Wang
  • Patent number: 11018099
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a semiconductor chip; a substrate facing an active surface of the semiconductor chip; and a conductive bump extending from the active surface of the semiconductor chip toward the substrate, wherein the conductive bump comprises: a plurality of bump segments comprising a first group of bump segments and a second group of bump segments, wherein each bump segment comprises the same segment height in a direction orthogonal to the active surface of the semiconductor chip, and each bump segment comprises a volume defined by the multiplication of the segment height with the average cross-sectional area of the bump segment; wherein the ratio of the total volume of the first group of bump segments to the total volume of the second group of bump segments is between about 0.03 and about 0.8.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: May 25, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Pei-Haw Tsao, An-Tai Xu, Huang-Ting Hsiao, Kuo-Chin Chang
  • Publication number: 20210134635
    Abstract: The current disclosure describes carrier tape systems, which include a carrier tape including a plurality of pockets. Each pocket contains a semiconductor device adhered to a bottom surface of the pocket by an adhesive. In some embodiments, the adhesive is a reversible adhesive. Use of the adhesive reduces the likelihood the semiconductor device will be damaged due to movement of the semiconductor device in the pocket during shipment of the carrier tape. Methods of forming a semiconductor device carrier systems and methods of supplying semiconductor devices are also described.
    Type: Application
    Filed: October 30, 2019
    Publication date: May 6, 2021
    Inventors: Chen-Ming Kuo, Jing Ruei Lu, Pei-Haw Tsao
  • Publication number: 20210098327
    Abstract: Generally, the present disclosure provides example embodiments relating to a package that may be attached to a printed circuit board (PCB). In an embodiment, a structure includes a package. The package includes one or more dies and metal pads on an exterior surface of the package. At least some of the metal pads are first solder ball pads. The structure further includes pins, and each of the pins is attached to a respective one of the metal pads.
    Type: Application
    Filed: December 14, 2020
    Publication date: April 1, 2021
    Inventors: Pei-Haw Tsao, Tsung-Hsing Lu, Li-Huan Chu
  • Publication number: 20210035920
    Abstract: A non-conductive magnetic shield material is provided for use in magnetic shields of semiconductor packaging. The material is made magnetic by the incorporation of ferromagnetic particles into a polymer matrix, and is made non-conductive by the provision of an insulating coating on the ferromagnetic particles.
    Type: Application
    Filed: October 21, 2020
    Publication date: February 4, 2021
    Inventors: Tsung-Hsing LU, Pei-Haw TSAO, Li-Huan CHU
  • Patent number: 10912194
    Abstract: Generally, the present disclosure provides example embodiments relating to a printed circuit board (PCB). In an embodiment, a structure includes a PCB including insulating layers with respective metal layers being disposed therebetween. Each of first layers of the insulating layers includes a first fiberglass content. A second layer of the insulating layers has a second fiberglass content less than the first fiberglass content. For example, in some embodiments, the second insulating layer does not include a fiberglass matrix.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: February 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Haw Tsao, Tsung-Hsing Lu, Li-Huan Chu
  • Patent number: 10892230
    Abstract: A non-conductive magnetic shield material is provided for use in magnetic shields of semiconductor packaging. The material is made magnetic by the incorporation of ferromagnetic particles into a polymer matrix, and is made non-conductive by the provision of an insulating coating on the ferromagnetic particles.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: January 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Hsing Lu, Pei-Haw Tsao, Li-Huan Chu