Abstract: Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.

Abstract: In an embodiment, a device includes: a package component including: integrated circuit dies; an encapsulant around the integrated circuit dies; a redistribution structure over the encapsulant and the integrated circuit dies, the redistribution structure being electrically coupled to the integrated circuit dies; sockets over the redistribution structure, the sockets being electrically coupled to the redistribution structure; and a support ring over the redistribution structure and surrounding the sockets, the support ring being disposed along outermost edges of the redistribution structure, the support ring at least partially laterally overlapping the redistribution structure.

Abstract: A method for forming a semiconductor device, includes: forming a metal layer on a semiconductor substrate; forming a dielectric layer over the metal layer; etching a top portion of the dielectric layer; after etching the top portion of the dielectric layer, removing first mist from a bottom portion of the dielectric layer; removing the bottom portion of the dielectric layer to expose the metal layer; performing a pre-clean operation, using an alcohol base vapor or an aldehyde base vapor, on the dielectric layer and the metal layer; and forming a conductor extending through the dielectric layer and in contact with the metal layer.

Abstract: The present disclosure provides an acid resistant capsule shell composition including pectin with a degree of esterification (DE) of about 15% to about 40%, and a degree of amidation (DA) of greater than 0% to about 25%; and a divalent cation. An acid resistant capsule shell and a method for manufacturing the acid resistant capsule shell are also provided in the present disclosure.

Abstract: A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A core layer and a dielectric layer are sequentially stacked over the package array. The core layer includes a plurality of cavities. A plurality of first conductive patches is formed on the dielectric layer above the cavities.

Abstract: Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.

Abstract: Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.

Abstract: A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A dielectric layer having a core layer formed thereon is provided. The core layer includes a plurality of cavities penetrating through the core layer. The dielectric layer and the core layer are attached onto the package array such that the core layer is located between the dielectric layer and the package array. A plurality of first conductive patches is formed on the dielectric layer above the cavities.

Abstract: In a method for manufacturing a semiconductor device, a substrate is provided. Various first metal layers are formed on the substrate. A dielectric structure with through holes is formed over the first metal layers. The through holes expose the first metal layers. A pre-clean operation is performed on the dielectric structure and the first metal layers by using an alcohol base vapor and/or an aldehyde base vapor as a reduction agent. Conductors are formed on the first metal layers. In forming the conductors, the through holes are filled with the conductors.

Abstract: In an embodiment, a device includes: a package component including integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure over the encapsulant and the integrated circuit dies, and sockets over the redistribution structure; a mechanical brace physically coupled to the sockets, the mechanical brace having openings, each one of the openings exposing a respective one of the sockets; a thermal module physically and thermally coupled to the encapsulant and the integrated circuit dies; and bolts extending through the thermal module, the mechanical brace, and the package component.

Abstract: The present disclosure provides a method and a system for scanning wafer. The system captures a defect image of a wafer, and generates a reference image corresponding to the first defect image based on a reference image generation model. The system generates a defect marked image based on the defect image and the reference image.

Abstract: A method for inline inspection during semiconductor wafer fabrication is provided. The method includes forming a plurality of test structures on a semiconductor wafer along two opposite directions. An offset distance between a sample feature and a target feature of each of the test structures increases gradually along the two opposite directions. The method further includes producing an image of the test structures. The method also includes performing image analysis of the image to recognize a position with an extreme of a gray level. In addition, the method includes calculating an overlay error according to the recognized position.

Abstract: An electronic device and a manufacturing method thereof are provided. The electronic device includes a chip package, a core dielectric layer disposed on the chip package, and an antenna pattern disposed on the core dielectric layer opposite to the chip package. The chip package includes a semiconductor chip, an insulating encapsulation encapsulating the semiconductor chip, and a redistribution structure electrically coupled to the semiconductor chip. The redistribution structure includes a first circuit pattern located at an outermost side of the chip package, and a patterned dielectric layer disposed between the first circuit pattern and the insulating encapsulation. The core dielectric layer is in contact with the first circuit pattern. The core dielectric layer and the patterned dielectric layer are of different materials. The antenna pattern is electrically coupled to the chip package.

Abstract: A method includes: coupling a first end of a first conductive trace to a free electron source; scanning exposed surfaces of the first and a second conductive traces with an electron beam, the first conductive trace and a second conductive trace being alternately arranged and spaced apart; obtaining an image of the first conductive trace and the second conductive trace while performing the scanning; and determining a routing characteristic of the first conductive trace and the second conductive trace based on the image.

Abstract: The present invention relates to a modified starch and a method for obtaining the modified starch by using a debranching enzyme, such as isoamylase, pullulanase, limit dextrinase and the like. The debranching enzyme modified starch of present invention exhibits excellent film-forming capacity, film strength, and gelation ability, so as to be used as a material for making hard capsules without the use of coagulants and plasticizers.

Abstract: A method for inline inspection during semiconductor wafer fabrication is provided. The method includes forming a plurality of test structures on a semiconductor wafer along two opposite directions. An offset distance between a sample feature and a target feature of each of the test structures increases gradually along the two opposite directions. The method further includes producing an image of the test structures. The method also includes performing image analysis of the image to recognize a position with an extreme of a gray level. In addition, the method includes calculating an overlay error according to the recognized position.

Abstract: A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A dielectric layer having a core layer formed thereon is provided. The core layer includes a plurality of cavities penetrating through the core layer. The dielectric layer and the core layer are attached onto the package array such that the core layer is located between the dielectric layer and the package array. A plurality of first conductive patches is formed on the dielectric layer above the cavities.

Abstract: The present disclosure provides an acid resistant capsule shell composition including pectin with a degree of esterification (DE) of about 15% to about 40%, and a degree of amidation (DA) of greater than 0% to about 25%; and a divalent cation. An acid resistant capsule shell and a method for manufacturing the acid resistant capsule shell are also provided in the present disclosure.

Abstract: A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A dielectric layer and a core material layer are sequentially formed on a first carrier. A portion of the core material layer is removed to form a core layer having a plurality of cavities. The first carrier, the dielectric layer, and the core layer are attached onto the package array such that the core layer is located between the dielectric layer and the package array. The first carrier is removed from the dielectric layer. A plurality of first conductive patches is formed on the dielectric layer above the cavities.

Abstract: A method for inline inspection during semiconductor wafer fabrication is provided. The method includes forming a plurality of test structures on a semiconductor wafer along two opposite directions. An offset distance between a sample feature and a target feature of each of the test structures increases gradually along the two opposite directions. The method further includes producing an image of the test structures. The method also includes performing image analysis of the image to recognize a position with an extreme of a gray level. In addition, the method includes calculating an overlay error according to the recognized position.