Patents by Inventor Pei-Jen LO
Pei-Jen LO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230378113Abstract: An electronic device, a package structure and an electronic manufacturing method are provided. The electronic device includes a substrate, a first bump, a second bump and a first reflowable material. The first bump is disposed over the substrate, and has a first width. An end portion of the first bump defines a first recess portion. The second bump is disposed over the substrate, and has a second width less than the first width. The first reflowable material is disposed on the first bump and extends in the first recess portion.Type: ApplicationFiled: August 1, 2023Publication date: November 23, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventor: Pei-Jen LO
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Patent number: 11715716Abstract: An electronic device, a package structure and an electronic manufacturing method are provided. The electronic device includes a substrate, a first bump, a second bump and a first reflowable material. The first bump is disposed over the substrate, and has a first width. An end portion of the first bump defines a first recess portion. The second bump is disposed over the substrate, and has a second width less than the first width. The first reflowable material is disposed on the first bump and extends in the first recess portion.Type: GrantFiled: July 16, 2021Date of Patent: August 1, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventor: Pei-Jen Lo
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Publication number: 20230061684Abstract: An electronic package structure, an electronic substrate, and a method of manufacturing an electronic package structure are provided. The electronic package structure includes a substrate. The substrate includes a bonding region and an alignment structure. The bonding region is located at a side of the substrate and configured to bond with an electronic component. The alignment structure is located at the side of the substrate and out of the bonding region and configured to providing a fiducial mark for position-aligning, wherein the alignment structure comprises a first region and a second region visually distinct from the first region.Type: ApplicationFiled: August 27, 2021Publication date: March 2, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Shun-Tsat TU, Pei-Jen LO
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Patent number: 11594506Abstract: A semiconductor package is provided. The semiconductor package includes a first conductive layer, a plurality of first conductive pads, a plurality of second conductive pads, and a first dielectric layer. The first conductive pads are electrically connected to the first conductive layer. The second conductive pads are electrically disconnected from the first conductive layer.Type: GrantFiled: September 23, 2020Date of Patent: February 28, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Pei-Jen Lo, Shun-Tsat Tu, Cheng-En Weng
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Publication number: 20230018031Abstract: An electronic device, a package structure and an electronic manufacturing method are provided. The electronic device includes a substrate, a first bump, a second bump and a first reflowable material. The first bump is disposed over the substrate, and has a first width. An end portion of the first bump defines a first recess portion. The second bump is disposed over the substrate, and has a second width less than the first width. The first reflowable material is disposed on the first bump and extends in the first recess portion.Type: ApplicationFiled: July 16, 2021Publication date: January 19, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventor: Pei-Jen LO
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Patent number: 11538756Abstract: A bonding structure is provided. The bonding structure includes a conductive layer, a seed layer, and a nanotwinned copper (NT-Cu) layer. The seed layer is disposed on the conductive layer. The NT-Cu layer is disposed on the seed layer. The NT-Cu layer has anisotropic crystal structure.Type: GrantFiled: September 16, 2020Date of Patent: December 27, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Shun-Tsat Tu, Pei-Jen Lo, Chien-Han Chiu
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Patent number: 11393776Abstract: A semiconductor device package includes a substrate, a first coil, a dielectric layer and a second coil. The first coil is disposed on the substrate. The first coil includes a first conductive segment and a second conductive segment. The dielectric layer covers the first conductive segment of the first coil and the second conductive segment of the first coil and defines a first recess between the first conductive segment of the first coil and the second conductive segment of the first coil. The second coil is disposed on the dielectric layer. The second coil has a first conductive segment disposed within the first recess.Type: GrantFiled: May 17, 2018Date of Patent: July 19, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Shun-Tsat Tu, Pei-Jen Lo, Yan-Si Lin, Chien-Chi Kuo
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Publication number: 20220093548Abstract: A semiconductor package is provided. The semiconductor package includes a first conductive layer, a plurality of first conductive pads, a plurality of second conductive pads, and a first dielectric layer. The first conductive pads are electrically connected to the first conductive layer. The second conductive pads are electrically disconnected from the first conductive layer.Type: ApplicationFiled: September 23, 2020Publication date: March 24, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Pei-Jen LO, Shun-Tsat TU, Cheng-En WENG
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Publication number: 20220084951Abstract: A bonding structure is provided. The bonding structure includes a conductive layer, a seed layer, and a nanotwinned copper (NT-Cu) layer. The seed layer is disposed on the conductive layer. The NT-Cu layer is disposed on the seed layer. The NT-Cu layer has anisotropic crystal structure.Type: ApplicationFiled: September 16, 2020Publication date: March 17, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Shun-Tsat TU, Pei-Jen LO, Chien-Han CHIU
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Publication number: 20210320038Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a substrate having a central region and a periphery surrounding the central region, and an electronic component disposed on the substrate. The substrate includes a plurality of testing contacts disposed within the periphery and spaced apart from each other. The electronic component includes a dummy pad. The dummy pad covers two of the plurality of the testing contacts and laterally spaced apart from the other of the plurality of the testing contacts. A method of semiconductor device package alignment inspection is also provided.Type: ApplicationFiled: April 9, 2020Publication date: October 14, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Ting Wei HSU, Pei-Jen LO, Shun-Tsat TU
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Patent number: 11120988Abstract: A semiconductor device package includes a first semiconductor device, a first redistribution layer (RDL) structure and a second RDL structure. The first semiconductor device has a first conductive terminal and a second conductive terminal. The first RDL structure covers the first conductive terminal. The second RDL structure covers the second conductive terminal and being separated from the first RDL structure.Type: GrantFiled: August 1, 2019Date of Patent: September 14, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Pei-Jen Lo, Cheng-Lung She
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Patent number: 11031382Abstract: An electronic device includes: a first insulation layer and a first conductive pillar. The first insulation layer has a first surface and a second surface opposite to the first surface, and the first conductive pillar comprises a first portion and a second portion. The first portion of the first conductive pillar is surrounded by the first insulation layer. The second portion of the first conductive pillar is disposed on the first surface of the first insulation layer. A height of the second portion of the first conductive pillar is equal to or greater than 10% of a height of the first portion of the conductive pillar.Type: GrantFiled: October 3, 2018Date of Patent: June 8, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Pei-Jen Lo, Chien-Han Chiu, Wen Hung Huang
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Patent number: 11011491Abstract: A semiconductor device package includes a connection structure having a first portion and a second portion extending from the first portion, the second portion having a width less than the first portion; and a dielectric layer surrounding the connection structure, wherein the dielectric layer and the second portion of the connection structure defines a space.Type: GrantFiled: September 6, 2019Date of Patent: May 18, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Shun-Tsat Tu, Pei-Jen Lo, Fong Ren Sie, Cheng-En Weng, Min Lung Huang
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Publication number: 20210074669Abstract: A semiconductor device package includes a connection structure having a first portion and a second portion extending from the first portion, the second portion having a width less than the first portion; and a dielectric layer surrounding the connection structure, wherein the dielectric layer and the second portion of the connection structure defines a space.Type: ApplicationFiled: September 6, 2019Publication date: March 11, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Shun-Tsat TU, Pei-Jen LO, Fong Ren SIE, Cheng-En WENG, Min Lung HUANG
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Publication number: 20210035794Abstract: A semiconductor device package includes a first semiconductor device, a first redistribution layer (RDL) structure and a second RDL structure. The first semiconductor device has a first conductive terminal and a second conductive terminal. The first RDL structure covers the first conductive terminal. The second RDL structure covers the second conductive terminal and being separated from the first RDL structure.Type: ApplicationFiled: August 1, 2019Publication date: February 4, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Pei-Jen LO, Cheng-Lung SHE
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Publication number: 20200111774Abstract: An electronic device includes: a first insulation layer and a first conductive pillar. The first insulation layer has a first surface and a second surface opposite to the first surface, and the first conductive pillar comprises a first portion and a second portion. The first portion of the first conductive pillar is surrounded by the first insulation layer. The second portion of the first conductive pillar is disposed on the first surface of the first insulation layer. A height of the second portion of the first conductive pillar is equal to or greater than 10% of a height of the first portion of the conductive pillar.Type: ApplicationFiled: October 3, 2018Publication date: April 9, 2020Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Pei-Jen LO, Chien-Han CHIU, Wen Hung HUANG
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Publication number: 20190355676Abstract: A semiconductor device package includes a substrate, a first coil, a dielectric layer and a second coil. The first coil is disposed on the substrate. The first coil includes a first conductive segment and a second conductive segment. The dielectric layer covers the first conductive segment of the first coil and the second conductive segment of the first coil and defines a first recess between the first conductive segment of the first coil and the second conductive segment of the first coil. The second coil is disposed on the dielectric layer. The second coil has a first conductive segment disposed within the first recess.Type: ApplicationFiled: May 17, 2018Publication date: November 21, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Shun-Tsat TU, Pei-Jen LO, Yan-Si LIN, Chien-Chi KUO