Patents by Inventor Pei-Ren Jeng

Pei-Ren Jeng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170167021
    Abstract: The present disclosure provides a semiconductor fabrication apparatus in accordance with one embodiment. The apparatus includes a processing chamber; a wafer stage configured in the processing chamber, the wafer stage is operable to secure and rotate a plurality of wafers around an axis; a first chemical delivery mechanism configured in the processing chamber to provide a first chemical to a first reaction zone in the processing chamber; and a second chemical delivery mechanism configured in the processing chamber to provide a second chemical to a second reaction zone in the processing chamber. The second chemical delivery mechanism includes an edge chemical injector and a first radial chemical injector.
    Type: Application
    Filed: June 1, 2016
    Publication date: June 15, 2017
    Inventors: Anthony Lin, Ching-Lun Lai, Pei-Ren Jeng, Tze-Liang Lee
  • Patent number: 9647066
    Abstract: A FinFET device may include a dummy FinFET structure laterally adjacent an active FinFET structure to reduce stress imbalance and the effects of stress imbalance on the active FinFET structure. The FinFET device comprises an active FinFET comprising a plurality of semiconductor fins, and a dummy FinFET comprising a plurality of semiconductor fins. The active FinFET and the dummy FinFET are laterally spaced from each other by a spacing that is related to the fin pitch of the active FinFET.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: May 9, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chang-Shen Lu, Chih-Tang Peng, Tai-Chun Huang, Pei-Ren Jeng, Hao-Ming Lien, Yi-Hung Lin, Tze-Liang Lee, Syun-Ming Jang
  • Publication number: 20170110312
    Abstract: An apparatus includes a vacuum chamber, a wafer transfer mechanism, a first gas source, a second gas source and a reuse gas pipe. The vacuum chamber is divided into at least three reaction regions including a first reaction region, a second reaction region and a third reaction region. The wafer transfer mechanism is structured to transfer a wafer from the first reaction region to the third reaction region via the second reaction region. The first gas source supplies a first gas to the first reaction region via a first gas pipe, and a second gas source supplies a second gas to the second reaction region via a second gas pipe. The reuse gas pipe is connected between the first reaction region and the third reaction region for supplying an unused first gas collected in the first reaction region to the third reaction region.
    Type: Application
    Filed: October 20, 2015
    Publication date: April 20, 2017
    Inventors: Tsai-Fu HSIAO, Kuang-Yuan HSU, Pei-Ren JENG, Tze-Liang LEE
  • Patent number: 9548366
    Abstract: An embodiment is a method including forming a first gate over a substrate, the first gate having first gate spacers on opposing sidewalls, forming a first hard mask layer over the first gate, forming a second hard mask layer over the first hard mask layer, the second hard mask layer having a different material composition than the first hard mask layer, forming a first dielectric layer adjacent and over the first gate, etching a first opening through the first dielectric layer to expose a portion of the substrate, at least a portion of the second hard mask layer being exposed in the first opening, filling the first opening with a conductive material, and removing the second hard mask layer and the portions of the conductive material and first dielectric layer above the first hard mask layer to form a first conductive contact in the remaining first dielectric layer.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: January 17, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsai-Jung Ho, Kuang-Yuan Hsu, Pei-Ren Jeng
  • Publication number: 20160240408
    Abstract: A method includes performing an anneal on a wafer. The wafer includes a wafer-edge region, and an inner region encircled by the wafer-edge region. During the anneal, a first power applied on a portion of the wafer-edge region is at least lower than a second power for annealing the inner region.
    Type: Application
    Filed: April 26, 2016
    Publication date: August 18, 2016
    Inventors: Yi-Chao Wang, Yu-Chang Lin, Li-Ting Wang, Tai-Chun Huang, Pei-Ren Jeng, Tze-Liang Lee
  • Publication number: 20160196979
    Abstract: An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, a metal gate structure over the semiconductor substrate and the gate dielectric, a dielectric film on the metal gate structure, the dielectric film comprising oxynitride combined with metal from the metal gate, and an interlayer dielectric (ILD) on either side of the metal gate structure.
    Type: Application
    Filed: January 6, 2016
    Publication date: July 7, 2016
    Inventors: Jin-Aun Ng, Bao-Ru Young, Harry-Hak-Lay Chuang, Maxi Chang, Chih-Tang Peng, Chih-Yang Yeh, Ta-Wei Lin, Huan-Just Lin, Hui-Wen Lin, Jen-Sheng Yang, Pei-Ren Jeng, Jung-Hui Kao, Shih-Hao Lo, Yuan-Tien Tu
  • Publication number: 20160163836
    Abstract: A FinFET includes a substrate, a fin structure on the substrate, a source in the fin structure, a drain in the fin structure, a channel in the fin structure between the source and the drain, a gate dielectric layer over the channel, and a gate over the gate dielectric layer. At least one of the source and the drain includes a bottom SiGe layer.
    Type: Application
    Filed: February 15, 2016
    Publication date: June 9, 2016
    Inventors: Ming-Hua Yu, Pei-Ren Jeng, Tze-Liang Lee
  • Patent number: 9337059
    Abstract: A method includes performing an anneal on a wafer. The wafer includes a wafer-edge region, and an inner region encircled by the wafer-edge region. During the anneal, a first power applied on a portion of the wafer-edge region is at least lower than a second power for annealing the inner region.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: May 10, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Chao Wang, Yu-Chang Lin, Li-Ting Wang, Tai-Chun Huang, Pei-Ren Jeng, Tze-Liang Lee
  • Patent number: 9293581
    Abstract: A FinFET includes a substrate, a fin structure on the substrate, a source in the fin structure, a drain in the fin structure, a channel in the fin structure between the source and the drain, a gate dielectric layer over the channel, and a gate over the gate dielectric layer. At least one of the source and the drain includes a bottom SiGe layer.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: March 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hua Yu, Pei-Ren Jeng, Tze-Liang Lee
  • Patent number: 9252224
    Abstract: An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, a metal gate structure over the semiconductor substrate and the gate dielectric, a dielectric film on the metal gate structure, the dielectric film comprising oxynitride combined with metal from the metal gate, and an interlayer dielectric (ILD) on either side of the metal gate structure.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: February 2, 2016
    Assignee: Taiwan semiconductor Manufacturing Company, Ltd.
    Inventors: Jin-Aun Ng, Maxi Chang, Jen-Sheng Yang, Ta-Wei Lin, Shih-Hao Lo, Chih-Yang Yeh, Hui-Wen Lin, Jung-Hui Kao, Yuan-Tien Tu, Huan-Just Lin, Chih-Tang Peng, Pei-Ren Jeng, Bao-Ru Young, Harry-Hak-Lay Chuang
  • Publication number: 20160013095
    Abstract: A method includes performing a plasma treatment on a first surface of a first material and a second surface of a second material simultaneously, wherein the first material is different from the second material. A third material is formed on treated first surface of the first material and on treated second surface of the second material. The first, the second, and the third materials may include a hard mask, a semiconductor material, and an oxide, respectively.
    Type: Application
    Filed: September 21, 2015
    Publication date: January 14, 2016
    Inventors: Yu-Ling Liou, Chih-Tang Peng, Pei-Ren Jeng, Hao-Ming Lien, Tze-Liang Lee
  • Patent number: 9142402
    Abstract: A method includes performing a plasma treatment on a first surface of a first material and a second surface of a second material simultaneously, wherein the first material is different from the second material. A third material is formed on treated first surface of the first material and on treated second surface of the second material. The first, the second, and the third materials may include a hard mask, a semiconductor material, and an oxide, respectively.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: September 22, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Ling Liou, Chih-Tang Peng, Pei-Ren Jeng, Hao-Ming Lien, Tze-Liang Lee
  • Publication number: 20150221509
    Abstract: A method includes forming a recess in a semiconductor substrate, the recess being adjacent to a gate stack, performing an epitaxial growth process within the recess to form a straining region, and forming a defect within the straining region in-situ with the epitaxial growth process.
    Type: Application
    Filed: February 6, 2014
    Publication date: August 6, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsiu-Ting Chen, Yi-Ming Huang, Shih-Chieh Chang, Hsing-Chi Chen, Pei-Ren Jeng
  • Publication number: 20150137180
    Abstract: A FinFET includes a substrate, a fin structure on the substrate, a source in the fin structure, a drain in the fin structure, a channel in the fin structure between the source and the drain, a gate dielectric layer over the channel, and a gate over the gate dielectric layer. At least one of the source and the drain includes a bottom SiGe layer.
    Type: Application
    Filed: January 27, 2015
    Publication date: May 21, 2015
    Inventors: Ming-Hua Yu, Pei-Ren Jeng, Tze-Liang Lee
  • Patent number: 8963258
    Abstract: A FinFET includes a substrate, a fin structure on the substrate, a source in the fin structure, a drain in the fin structure, a channel in the fin structure between the source and the drain, a gate dielectric layer over the channel, and a gate over the gate dielectric layer. At least one of the source and the drain includes a bottom SiGe layer.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: February 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Ming-Hua Yu, Pei-Ren Jeng, Tze-Liang Lee
  • Publication number: 20140367802
    Abstract: An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, a metal gate structure over the semiconductor substrate and the gate dielectric, a dielectric film on the metal gate structure, the dielectric film comprising oxynitride combined with metal from the metal gate, and an interlayer dielectric (ILD) on either side of the metal gate structure.
    Type: Application
    Filed: August 28, 2014
    Publication date: December 18, 2014
    Inventors: Jin-Aun Ng, Maxi Chang, Jen-Sheng Yang, Ta-Wei Lin, Shih-Hao Lo, Chih-Yang Yeh, Hui-Wen Lin, JUNG-HUI KAO, Yuan-Tien Tu, HUAN-JUST LIN, Chih-Tang Peng, Pei-Ren Jeng, BAO-RU YOUNG, HARRY-HAK-LA Y CHUANG
  • Publication number: 20140264590
    Abstract: A FinFET includes a substrate, a fin structure on the substrate, a source in the fin structure, a drain in the fin structure, a channel in the fin structure between the source and the drain, a gate dielectric layer over the channel, and a gate over the gate dielectric layer. At least one of the source and the drain includes a bottom SiGe layer.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 18, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Hua Yu, Pei-Ren Jeng, Tze-Liang Lee
  • Publication number: 20140252489
    Abstract: A method of forming a FinFET with a rounded source/drain profile comprises forming a fin in a substrate, etching a source/drain recess in the fin, forming a plurality of source/drain layers in the source/drain recess; and etching at least one of the plurality of source/drain layers. The source/drain layers may be a silicon germanium compound. Etching at the source/drain layers may comprises partially etching each of the plurality of source/drain layers prior to forming subsequent layers of the plurality of source/drain layers. The source/drain layers may be formed with a thickness at a top corner of about 15 nm, and the source/drain layers may each be etched back by about 3 nm prior to forming subsequent layers of the plurality of source/drain layers. Forming the plurality of source/drain layers optionally comprises forming at least five source/drain layers.
    Type: Application
    Filed: March 11, 2013
    Publication date: September 11, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hua Yu, Chih-Pin Tsao, Pei-Ren Jeng, Tze-Liang Lee
  • Patent number: 8822283
    Abstract: A method of making an integrated circuit includes providing a semiconductor substrate and forming a gate dielectric over the substrate, such as a high-k dielectric. A metal gate structure is formed over the semiconductor substrate and the gate dielectric and a thin dielectric film is formed over that. The thin dielectric film includes oxynitride combined with metal from the metal gate. The method further includes providing an interlayer dielectric (ILD) on either side of the metal gate structure.
    Type: Grant
    Filed: September 24, 2011
    Date of Patent: September 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jin-Aun Ng, Maxi Chang, Jen-Sheng Yang, Ta-Wei Lin, Shih-Hao Lo, Chih-Yang Yeh, Hui-Wen Lin, Jung-Hui Kao, Yuan-Tien Tu, Huan-Just Lin, Chih-Tang Peng, Pei-Ren Jeng, Bao-Ru Young, Hak-Lay Chuang
  • Patent number: 8796124
    Abstract: The present disclosure provides a method to dope fins of a semiconductor device. The method includes forming a first doping film on a first fin and forming a second doping film on the second fin. The first and second doping films include a different dopant type (e.g., n-type and p-type). An anneal process is performed which drives a first dopant from the first doping film into the first fin and drives a second dopant from the second doping film into the second fin. In an embodiment, the first and second dopants are driven into the sidewall of the respective fin.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: August 5, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Pei-Ren Jeng