Patents by Inventor Pei-Ren Jeng

Pei-Ren Jeng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8580653
    Abstract: A method of fabricating an isolation structure including forming a trench in a top surface of a substrate and partially filling the trench with a first oxide, wherein the first oxide is a pure oxide. Partially filling the trench includes forming a liner layer in the trench and forming the first oxide over the liner layer using silane and oxygen precursors at a pressure less than 10 milliTorr (mTorr) and a temperature ranging from about 500° C. to about 1000° C. The method further includes producing a solid reaction product in a top portion of the first oxide. The method further includes sublimating the solid reaction product by heating the substrate in a chamber at a temperature from 100° C. to 200° C. and removing the sublimated solid reaction product by flowing a carrier gas over the substrate. The method further includes filling the trench with a second oxide.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: November 12, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tze-Liang Lee, Pei-Ren Jeng, Chu-Yun Fu, Chyi Shyuan Chern, Jui-Hei Huang, Chih-Tang Peng, Hao-Ming Lien
  • Patent number: 8574995
    Abstract: The present disclosure provides methods of semiconductor device fabrication for 3D devices. One method includes provide a substrate having a recess and forming a doping layer on the substrate and in the recess. The substrate is then annealed. The annealing drives dopants of a first type from the doping layer into the substrate. This can form a doped region that may be the source/drain extension of the 3D device. An epitaxial region is then grown in the recess. The epitaxial region can form the source/drain region of the 3D device.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: November 5, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Pei-Ren Jeng
  • Publication number: 20130277760
    Abstract: A FinFET device may include a dummy FinFET structure laterally adjacent an active FinFET structure to reduce stress imbalance and the effects of stress imbalance on the active FinFET structure. The FinFET device comprises an active FinFET comprising a plurality of semiconductor fins, and a dummy FinFET comprising a plurality of semiconductor fins. The active FinFET and the dummy FinFET are laterally spaced from each other by a spacing that is related to the fin pitch of the active FinFET.
    Type: Application
    Filed: April 24, 2012
    Publication date: October 24, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chang-Shen Lu, Chih-Tang Peng, Tai-Chun Huang, Pei-Ren Jeng, Hao-Ming Lien, Yi-Hung Lin, Tze-Liang Lee, Syun-Ming Jang
  • Publication number: 20130171803
    Abstract: A method of fabricating an isolation structure including forming a trench in a top surface of a substrate and partially filling the trench with a first oxide, wherein the first oxide is a pure oxide. Partially filling the trench includes forming a liner layer in the trench and forming the first oxide over the liner layer using silane and oxygen precursors at a pressure less than 10 milliTorr (mTorr) and a temperature ranging from about 500° C. to about 1000° C. The method further includes producing a solid reaction product in a top portion of the first oxide. The method further includes sublimating the solid reaction product by heating the substrate in a chamber at a temperature from 100° C. to 200° C. and removing the sublimated solid reaction product by flowing a carrier gas over the substrate. The method further includes filling the trench with a second oxide.
    Type: Application
    Filed: February 25, 2013
    Publication date: July 4, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tze-Liang LEE, Pei-Ren JENG, Chu-Yun FU, Chyi Shyuan CHERN, Jui-Hei HUANG, Chih-Tang PENG, Hao-Ming LIEN
  • Publication number: 20130137251
    Abstract: A method includes performing a plasma treatment on a first surface of a first material and a second surface of a second material simultaneously, wherein the first material is different from the second material. A third material is formed on treated first surface of the first material and on treated second surface of the second material. The first, the second, and the third materials may include a hard mask, a semiconductor material, and an oxide, respectively.
    Type: Application
    Filed: November 30, 2011
    Publication date: May 30, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Ling Liou, Chih-Tang Peng, Pei-Ren Jeng, Hao-Ming Lien, Tze-Liang Lee
  • Publication number: 20130122676
    Abstract: The present disclosure provides methods of semiconductor device fabrication for 3D devices. One method includes provide a substrate having a recess and forming a doping layer on the substrate and in the recess. The substrate is then annealed. The annealing drives dopants of a first type from the doping layer into the substrate. This can form a doped region that may be the source/drain extension of the 3D device. An epitaxial region is then grown in the recess. The epitaxial region can form the source/drain region of the 3D device.
    Type: Application
    Filed: November 10, 2011
    Publication date: May 16, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd., ("TSMC")
    Inventor: Pei-Ren Jeng
  • Publication number: 20130102137
    Abstract: The present disclosure provides a method to dope fins of a semiconductor device. The method includes forming a first doping film on a first fin and forming a second doping film on the second fin. The first and second doping films include a different dopant type (e.g., n-type and p-type). An anneal process is performed which drives a first dopant from the first doping film into the first fin and drives a second dopant from the second doping film into the second fin. In an embodiment, the first and second dopants are driven into the sidewall of the respective fin.
    Type: Application
    Filed: October 25, 2011
    Publication date: April 25, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd., ("TSMC")
    Inventor: Pei-Ren Jeng
  • Patent number: 8404561
    Abstract: The invention relates to integrated circuit fabrication, and more particularly to an electronic device with an isolation structure made having almost no void. An exemplary method for fabricating an isolation structure, comprising: providing a substrate; forming a trench in the substrate; partially filling the trench with a first silicon oxide; exposing a surface of the first silicon oxide to a vapor mixture comprising NH3 and a fluorine-containing compound; heating the substrate to a temperature between 100° C. to 200° C.; and filling the trench with a second silicon oxide, whereby the isolation structure made has almost no void.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: March 26, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tze-Liang Lee, Pei-Ren Jeng, Chu-Yun Fu, Chyi Shyuan Chern, Jui-Hei Huang, Chih-Tang Peng, Hao-Ming Lien
  • Publication number: 20130056837
    Abstract: A method of making an integrated circuit includes providing a semiconductor substrate and forming a gate dielectric over the substrate, such as a high-k dielectric. A metal gate structure is formed over the semiconductor substrate and the gate dielectric and a thin dielectric film is formed over that. The thin dielectric film includes oxynitride combined with metal from the metal gate. The method further includes providing an interlayer dielectric (ILD) on either side of the metal gate structure.
    Type: Application
    Filed: September 24, 2011
    Publication date: March 7, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jin-Aun Ng, Maxi Chang, Jen-Sheng Yang, Ta-Wei Lin, Shih-Hao Lo, Chih-Yang Yeh, Hui-Wen Lin, Jung-Hui Kao, Yuan-Tien Tu, Huan-Just Lin, Chih-Tang Peng, Pei-Ren Jeng, Bao-Ru Young, Hak-Lay Chuang
  • Publication number: 20130052837
    Abstract: A method includes performing an anneal on a wafer. The wafer includes a wafer-edge region, and an inner region encircled by the wafer-edge region. During the anneal, a first power applied on a portion of the wafer-edge region is at least lower than a second power for annealing the inner region.
    Type: Application
    Filed: August 23, 2011
    Publication date: February 28, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Chao Wang, Yu-Chang Lin, Li-Ting Wang, Tai-Chun Huang, Pei-Ren Jeng, Tze-Liang Lee
  • Patent number: 7915173
    Abstract: A method for manufacturing a shallow trench isolation structure comprises etching a plurality of trenches into a silicon substrate. The trenches have an upright wall portion, a bottom floor portion, and a corner portion connecting the upright wall portion and the bottom floor portion. The method further comprises conformally depositing a dielectric layer into the trenches. The dielectric layer covers at least part of the upright wall portion, at least part of the bottom floor portion, and at least part of the corner portion. The method further comprises oxidizing the dielectric layer. A portion of the dielectric layer deposited over the corner portion is oxidized at a first oxidization rate, and a portion of the dielectric layer deposited over the upright wall portion is oxidized at a second oxidization rate. The first oxidization rate is less than the second oxidization rate. The method further comprises depositing an electrically insulating material into the trenches over the dielectric layer.
    Type: Grant
    Filed: May 5, 2005
    Date of Patent: March 29, 2011
    Assignee: Macronix International Co., Ltd.
    Inventor: Pei-Ren Jeng
  • Patent number: 7880213
    Abstract: A structure and a method of fabricating a bottom electrode of a metal-insulator-metal (MIM) capacitor are provided. First, a transition metal layer is formed on a substrate. Thereafter, a self-assembling polymer film having a nano-pattern is formed on the transition metal layer to expose a portion of the transition metal layer. Using the self-assembling polymer film as a mask, the exposed portion of the transition metal layer is treated to undergo a phase change so that the bottom electrode can achieve a nano-level of phase separation. Thereafter, the self-assembling polymer film is removed.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: February 1, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Wen-Miao Lo, Lurng-Sheng Lee, Pei-Ren Jeng, Cha-Hsin Lin, Ching-Chiun Wang
  • Publication number: 20100291751
    Abstract: The invention relates to integrated circuit fabrication, and more particularly to an electronic device with an isolation structure made having almost no void. An exemplary method for fabricating an isolation structure, comprising: providing a substrate; forming a trench in the substrate; partially filling the trench with a first silicon oxide; exposing a surface of the first silicon oxide to a vapor mixture comprising NH3 and a fluorine-containing compound; heating the substrate to a temperature between 100° C. to 200° C.; and filling the trench with a second silicon oxide, whereby the isolation structure made has almost no void.
    Type: Application
    Filed: May 5, 2010
    Publication date: November 18, 2010
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tze-Liang LEE, Pei-Ren JENG, Chu-Yun FU, Chyi Shyuan CHERN, Jui-Hei HUANG, Chih-Tang PENG, Hao-Ming LIEN
  • Patent number: 7723226
    Abstract: A bilayer porous low dielectric constant (low-k) interconnect structure and methods of fabricating the same are presented. A preferred embodiment having an effective dielectric constant of about 2.2 comprises a bottom deposited dielectric layer and a top deposited dielectric layer in direct contact with the former. The bottom layer and the top layer have same atomic compositions, but a higher dielectric constant value k. The bottom dielectric layer serves as an etch stop layer for the top dielectric layer, and the top dielectric layer can act as CMP stop layer. One embodiment of making the structure includes forming a bottom dielectric layer having a first porogen content and a top dielectric layer having a higher porogen content. A curing process leaves lower pore density in the bottom dielectric layer than that left in the top dielectric layer, which leads to higher dielectric value k in the bottom dielectric layer.
    Type: Grant
    Filed: January 17, 2007
    Date of Patent: May 25, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Yung-Cheng Lu, Pei-Ren Jeng, Chia-Cheng Chou, Keng-Chu Lin, Chung-Chi Ko, Tien-I Bao, Shwang-Ming Jeng
  • Patent number: 7683438
    Abstract: A nanocrystal memory element and a method for fabricating the same are proposed. The fabricating method involves selectively oxidizing polysilicon not disposed beneath and not covered with a plurality of metal nanocrystals, and leaving intact the polysilicon disposed beneath and thereby covered with the plurality of metal nanocrystals, with a view to forming double layered silicon-metal nanocrystals by self-alignment.
    Type: Grant
    Filed: May 22, 2008
    Date of Patent: March 23, 2010
    Assignee: Industrial Technology Research Institute
    Inventor: Pei-Ren Jeng
  • Patent number: 7446038
    Abstract: An interlayer interconnect structure of a three-dimensional memory includes memory cell groups, each composed of a plurality of memory cells and connected to their respective selection transistors, because of special arrangement of lines and first plugs as well as line layouts. The line layouts involve disposing a plurality of lines on each of a plurality of horizontal levels, and selectively forming second plugs between adjoining lines disposed on upper and lower horizontal levels, such that the plugs selectively connect the adjoining upper and lower lines to each other. Since identical layout patterns are adopted in individual stacking states of stacking layers disposed in the three-dimensional memory, the upper lines and the lower lines of the stacking layers of the three-dimensional memory share the same layouts, leading to a reduction in the number of masks used, simpler process adjustment, and lower costs.
    Type: Grant
    Filed: June 12, 2006
    Date of Patent: November 4, 2008
    Assignee: Industrial Technology Research Institute
    Inventor: Pei-Ren Jeng
  • Publication number: 20080217683
    Abstract: A nanocrystal memory element and a method for fabricating the same are proposed. The fabricating method involves selectively oxidizing polysilicon not disposed beneath and not covered with a plurality of metal nanocrystals, and leaving intact the polysilicon disposed beneath and thereby covered with the plurality of metal nanocrystals, with a view to forming double layered silicon-metal nanocrystals by self-alignment.
    Type: Application
    Filed: May 22, 2008
    Publication date: September 11, 2008
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventor: Pei-Ren Jeng
  • Publication number: 20080171431
    Abstract: A bilayer porous low dielectric constant (low-k) interconnect structure and methods of fabricating the same are presented. A preferred embodiment having an effective dielectric constant of about 2.2 comprises a bottom deposited dielectric layer and a top deposited dielectric layer in direct contact with the former. The bottom layer and the top layer have same atomic compositions, but a higher dielectric constant value k. The bottom dielectric layer serves as an etch stop layer for the top dielectric layer, and the top dielectric layer can act as CMP stop layer. One embodiment of making the structure includes forming a bottom dielectric layer having a first porogen content and a top dielectric layer having a higher porogen content. A curing process leaves lower pore density in the bottom dielectric layer than that left in the top dielectric layer, which leads to higher dielectric value k in the bottom dielectric layer.
    Type: Application
    Filed: January 17, 2007
    Publication date: July 17, 2008
    Inventors: Chen-Hua Yu, Yung-Cheng Lu, Pei-Ren Jeng, Chia-Cheng Chou, Keng-Chu Lin, Chung-Chi Ko, Tien-I Bao, Shwang-Ming Jeng
  • Patent number: 7393745
    Abstract: A nanocrystal memory element and a method for fabricating the same are proposed. The fabricating method involves selectively oxidizing polysilicon not disposed beneath and not covered with a plurality of metal nanocrystals, and leaving intact the polysilicon disposed beneath and thereby covered with the plurality of metal nanocrystals, with a view to forming double layered silicon-metal nanocrystals by self-alignment.
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: July 1, 2008
    Assignee: Industrial Technology Research Institute
    Inventor: Pei-Ren Jeng
  • Publication number: 20070178693
    Abstract: An interlayer interconnect structure of a three-dimensional memory includes memory cell groups, each composed of a plurality of memory cells and connected to their respective selection transistors, because of special arrangement of lines and first plugs as well as line layouts. The line layouts involve disposing a plurality of lines on each of a plurality of horizontal levels, and selectively forming second plugs between adjoining lines disposed on upper and lower horizontal levels, such that the plugs selectively connect the adjoining upper and lower lines to each other. Since identical layout patterns are adopted in individual stacking states of stacking layers disposed in the three-dimensional memory, the upper lines and the lower lines of the stacking layers of the three-dimensional memory share the same layouts, leading to a reduction in the number of masks used, simpler process adjustment, and lower costs.
    Type: Application
    Filed: June 12, 2006
    Publication date: August 2, 2007
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventor: Pei-Ren Jeng