Patents by Inventor Pei-Ren Jeng

Pei-Ren Jeng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070166911
    Abstract: A structure and a method of fabricating a bottom electrode of a metal-insulator-metal (MIM) capacitor are provided. First, a transition metal layer is formed on a substrate. Thereafter, a self-assembling polymer film having a nano-pattern is formed on the transition metal layer to expose a portion of the transition metal layer. Using the self-assembling polymer film as a mask, the exposed portion of the transition metal layer is treated to undergo a phase change so that the bottom electrode can achieve a nano-level of phase separation. Thereafter, the self-assembling polymer film is removed.
    Type: Application
    Filed: May 15, 2006
    Publication date: July 19, 2007
    Inventors: Wen-Miao Lo, Lurng-Sheng Lee, Pei-Ren Jeng, Cha-Hsin Lin, Ching-Chiun Wang
  • Publication number: 20070161162
    Abstract: A vertically-stacked three-dimensional nanocrystal memory device and a method for manufacturing the same is proposed. Each of the two vertically overlapping memory cells of the vertically-stacked three-dimensional nanocrystal memory device includes a thin-film transistor and nanocrystals embedded in a gate dielectric layer of the thin-film transistor. With the two vertically overlapping memory cells including, sharing and being controlled by a wordline, the bit density of the memory increases.
    Type: Application
    Filed: September 21, 2006
    Publication date: July 12, 2007
    Inventor: Pei-Ren Jeng
  • Publication number: 20070145344
    Abstract: A resistance-change nanocrystal memory is proposed, which includes at least one memory unit. The memory unit further includes a channel and nanocrystals embedded in the channel. Electric charges in the nanocrystals are accessed, by applying a voltage to the channel. Then, conductivity of the channel is altered by the electric charges stored in the nanocrystals. Eventually, electric current is measured while an additional transistor is on, so as to achieve memory functions.
    Type: Application
    Filed: July 31, 2006
    Publication date: June 28, 2007
    Inventor: Pei-Ren Jeng
  • Publication number: 20070105316
    Abstract: A nanocrystal memory element and a method for fabricating the same involves repeatedly and alternately depositing, by atomic layer deposition, conductive layers and dielectric layers on a substrate with a tunnel oxide layer formed thereon, forming multiple layers of nanocrystal groups as a result of crystallization of conductive layers in a rapid thermal annealing process, and forming a gate on the top dielectric layer. The nanocrystal groups disposed at any two neighboring levels are separated by one dielectric layer, thus a plurality of nanocrystals formed in an integration layer are disposed at the same level. Barrier widths between a channel and the nanocrystals of the nanocrystal groups disposed at the same level are equal. Therefore, the nanocrystals at the same level are subjected the same electric field when voltage is applied to the gate, resulting in improved transistor performance, enhanced control of threshold voltage, and avoidance of over-erasing.
    Type: Application
    Filed: July 31, 2006
    Publication date: May 10, 2007
    Applicant: Industrial Technology Research Institute
    Inventor: Pei-Ren Jeng
  • Publication number: 20070105307
    Abstract: A nanocrystal memory element and a method for fabricating the same are proposed. The fabricating method involves selectively oxidizing polysilicon not disposed beneath and not covered with a plurality of metal nanocrystals, and leaving intact the polysilicon disposed beneath and thereby covered with the plurality of metal nanocrystals, with a view to forming double layered silicon-metal nanocrystals by self-alignment.
    Type: Application
    Filed: August 3, 2006
    Publication date: May 10, 2007
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventor: Pei-Ren Jeng
  • Patent number: 7157360
    Abstract: A memory device with an improved passivation structure. The memory device includes a semiconductor substrate with memory units thereon, an interconnect structure over the surface of the semiconductor substrate to connect with the memory units, and a passivation structure over the surface of the interconnect structure. The passivation structure comprises a dielectric layer over the surface of the interconnect structure and a silicon-oxy-nitride (SiOxNy) layer over the surface of the dielectric layer.
    Type: Grant
    Filed: September 29, 2003
    Date of Patent: January 2, 2007
    Assignee: Macronix International Co., Ltd.
    Inventors: Hung-Yu Chiu, U-Way Tseng, Wen-Pin Lu, Cheng-Chen Huseh, Pei-Ren Jeng, Fu-Hsiang Hsu
  • Patent number: 7151042
    Abstract: A method of improving flash memory performance. The method includes: providing a substrate having a gate structure thereon, the gate structure having a gate dielectric layer, a first polysilicon layer, an interploy dielectric layer, and a second polysilicon layer; then, depositing an gate insulating layer to enclose the gate structure, for forming side wall spacers; next, performing a first anneal on the substrate and the enclosed gate structure; then, performing a cell reoxidation on the substrate and the enclosed gate structure by dilute oxidation process using mixed gas comprising oxygen O2 and nitrogen N2. The invention reduces encroachment issues in the interpoly dielectric layer and the tunnel oxide and improves gate coupling ratio (GCR).
    Type: Grant
    Filed: February 2, 2005
    Date of Patent: December 19, 2006
    Assignee: Macronix International Co., Ltd.
    Inventors: Pei-Ren Jeng, Hsuan-Ling Kao
  • Publication number: 20060252228
    Abstract: A method for manufacturing a shallow trench isolation structure comprises etching a plurality of trenches into a silicon substrate. The trenches have an upright wall portion, a bottom floor portion, and a corner portion connecting the upright wall portion and the bottom floor portion. The method further comprises conformally depositing a dielectric layer into the trenches. The dielectric layer covers at least part of the upright wall portion, at least part of the bottom floor portion, and at least part of the corner portion. The method further comprises oxidizing the dielectric layer. A portion of the dielectric layer deposited over the corner portion is oxidized at a first oxidization rate, and a portion of the dielectric layer deposited over the upright wall portion is oxidized at a second oxidization rate. The first oxidization rate is less than the second oxidization rate. The method further comprises depositing an electrically insulating material into the trenches over the dielectric layer.
    Type: Application
    Filed: May 5, 2005
    Publication date: November 9, 2006
    Inventor: Pei-Ren Jeng
  • Publication number: 20060172490
    Abstract: A method of improving flash memory performance. The method includes: providing a substrate having a gate structure thereon, the gate structure having a gate dielectric layer, a first polysilicon layer, an interploy dielectric layer, and a second polysilicon layer; then, depositing an gate insulating layer to enclose the gate structure, for forming side wall spacers; next, performing a first anneal on the substrate and the enclosed gate structure; then, performing a cell reoxidation on the substrate and the enclosed gate structure by dilute oxidation process using mixed gas comprising oxygen O2 and nitrogen N2. The invention reduces encroachment issues in the interpoly dielectric layer and the tunnel oxide and improves gate coupling ratio (GCR).
    Type: Application
    Filed: February 2, 2005
    Publication date: August 3, 2006
    Inventors: Pei-Ren Jeng, Hsuan-Ling Kao
  • Patent number: 6984553
    Abstract: In a manufacturing method for a shallow trench isolation, first, a multi-layer structure is formed over a semiconductor substrate. A first trench is formed in the multi-layer structure to define an isolation region and an active region. Sidewalls in the first trench are formed by depositing sidewall material over the multi-layer structure and surfaces of the first trench and etching the sidewall material. An isolation trench is then formed in the substrate by etching the substrate using the sidewalls and the multi-layer structure as a mask. Then the sidewalls are etched back to expose a portion of the substrate surface. Thermal oxidation is performed to oxidize the second trench, wherein the etched sidewalls and the multi-layer structure protect the substrate underneath from being oxidized. Then, the oxidized second trench is filled with a filling material and the whole structure is polished. The amount by which the sidewalls are etched back controls a bird beak that is formed in the active region.
    Type: Grant
    Filed: March 12, 2003
    Date of Patent: January 10, 2006
    Assignee: Macronix International Co., Ltd.
    Inventor: Pei-Ren Jeng
  • Patent number: 6939768
    Abstract: A method of forming self-aligned contacts that includes providing at least one stacked-gate structure on a semiconductor substrate, forming a first dielectric layer on the stacked-gate structure and the semiconductor substrate, forming a second dielectric layer on the first dielectric layer, the second dielectric layer being etch selective relative to the first dielectric layer, etching the second dielectric layer to expose a portion of the first dielectric layer formed on a top surface and along at least a portion of upper sidewalls of the stacked-gate structure, removing the exposed portion of the first dielectric layer, and forming a third dielectric layer on the sidewalls of the stacked-gate structure.
    Type: Grant
    Filed: April 1, 2003
    Date of Patent: September 6, 2005
    Assignee: Macronix International Co., Ltd.
    Inventor: Pei-Ren Jeng
  • Patent number: 6908814
    Abstract: A selfaligned process for a flash memory comprises applying a solution with a high etch selectivity to etch the sidewall of the tungsten silicide in the gate structure of the flash memory during a clean process before forming a spacer for the gate structure. This process prevents the gate structure from degradation caused by thermal stress.
    Type: Grant
    Filed: December 3, 2003
    Date of Patent: June 21, 2005
    Assignee: Macronix International Co., Ltd.
    Inventors: Pei-Ren Jeng, Lin-Wu Yang
  • Patent number: 6867466
    Abstract: A memory device with an improved passivation structure. The memory device includes a semiconductor substrate with memory units thereon, an interconnect structure over the surface of the semiconductor substrate to connect with the memory units, and a passivation structure over the surface of the interconnect structure. The passivation structure comprises a dielectric layer over the surface of the interconnect structure and a silicon-oxy-nitride (SiOxNy) layer over the surface of the dielectric layer.
    Type: Grant
    Filed: September 13, 2002
    Date of Patent: March 15, 2005
    Assignee: Macronix International Co., Ltd.
    Inventors: Hung-Yu Chiu, U-Way Tseng, Wen-Pin Lu, Cheng-Chen Huseh, Pei-Ren Jeng, Fu-Hsiang Hsu
  • Patent number: 6849504
    Abstract: A method for fabricating a flash memory is described. A stacked gate structure and a source/drain are formed on a substrate. An inter-layer dielectrics and a plurality of inter-metal dielectric layers are then formed over the substrate, wherein at least one layer among the inter-layer dielectrics and the inter-metal dielectric layers has a silicon carbide layer formed thereon. The silicon carbide layer is formed to protect the memory device from an UV irradiation, so as to prevent data errors occurring in the memory device.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: February 1, 2005
    Assignee: MACRONIX International Co., Ltd
    Inventors: Ping-Yi Chang, Pei-Ren Jeng
  • Publication number: 20040266105
    Abstract: A selfaligned process for a flash memory comprises applying a solution with a high etch selectivity to etch the sidewall of the tungsten silicide in the gate structure of the flash memory during a clean process before forming a spacer for the gate structure. This process prevents the gate structure from degradation caused by thermal stress.
    Type: Application
    Filed: December 3, 2003
    Publication date: December 30, 2004
    Inventors: Pei-Ren Jeng, Lin-Wu Yang
  • Publication number: 20040198006
    Abstract: A method of forming self-aligned contacts that includes providing at least one stacked-gate structure on a semiconductor substrate, forming a first dielectric layer on the stacked-gate structure and the semiconductor substrate, forming a second dielectric layer on the first dielectric layer, the second dielectric layer being etch selective relative to the first dielectric layer, etching the second dielectric layer to expose a portion of the first dielectric layer formed on a top surface and along at least a portion of upper sidewalls of the stacked-gate structure, removing the exposed portion of the first dielectric layer, and forming a third dielectric layer on the sidewalls of the stacked-gate structure.
    Type: Application
    Filed: April 1, 2003
    Publication date: October 7, 2004
    Applicant: Macronix International Co., Ltd.
    Inventor: Pei-Ren Jeng
  • Publication number: 20040180550
    Abstract: In a manufacturing method for a shallow trench isolation, first, a multi-layer structure is formed over a semiconductor substrate. A first trench is formed in the multi-layer structure to define an isolation region and an active region. Sidewalls in the first trench are formed by depositing sidewall material over the multi-layer structure and surfaces of the first trench and etching the sidewall material. An isolation trench is then formed in the substrate by etching the substrate using the sidewalls and the multi-layer structure as a mask. Then the sidewalls are etched back to expose a portion of the substrate surface. Thermal oxidation is performed to oxidize the second trench, wherein the etched sidewalls and the multi-layer structure protect the substrate underneath from being oxidized. Then, the oxidized second trench is filled with a filling material and the whole structure is polished. The amount by which the sidewalls are etched back controls a bird beak that is formed in the active region.
    Type: Application
    Filed: March 12, 2003
    Publication date: September 16, 2004
    Applicant: Macronix International Co.,Ltd.
    Inventor: Pei-Ren Jeng
  • Publication number: 20040166632
    Abstract: A method of fabricating a flash memory. A tunneling dielectric layer and a conductive layer are formed on a substrate. The conductive layer is patterned to form a floating gate. A source/drain region is formed in the substrate between the floating gates. A gate dielectric layer is formed. The gate dielectric layer includes an oxide layer formed on the floating gate by in-situ steam generation (ISSG). A control gate is formed on the gate dielectric layer.
    Type: Application
    Filed: February 24, 2003
    Publication date: August 26, 2004
    Inventors: PEI-REN JENG, TZUNG-TING HAN, JUNG-YU HSIEH, JUNE-MIN YAO
  • Publication number: 20040056360
    Abstract: A memory device with an improved passivation structure. The memory device includes a semiconductor substrate with memory units thereon, an interconnect structure over the surface of the semiconductor substrate to connect with the memory units, and a passivation structure over the surface of the interconnect structure. The passivation structure comprises a dielectric layer over the surface of the interconnect structure and a silicon-oxy-nitride (SiOxNy) layer over the surface of the dielectric layer.
    Type: Application
    Filed: September 29, 2003
    Publication date: March 25, 2004
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Hung-Yu Chiu, U-Way Tseng, Wen-Pin Lu, Cheng-Chen Huseh, Pei-Ren Jeng, Fu-Hsiang Hsu
  • Patent number: 6706611
    Abstract: A substrate is provided, and a dielectric layer is formed, thereon. Then a photoresist layer is formed on the dielectric layer and defined a predetermined region for ion implantation. Next, a dense region of dielectric layer is formed by retrograde implantation with photoresist layer as an ion implanted mask, wherein the dense region is a predetermined region for trench. A hard mask layer is formed on the dielectric layer after the photoresist layer is removed. Afterward forming and defining another photoresist layer on the hard mask layer to expose a partial surface of the hard mask layer as a trench region, wherein the partial surface of the hard mask layer comprises the dense region. Subsequently, an etching process is performed by means of the photoresist layer as the etched mask to etch through the hard mask layer and the dielectric layer until the substrate surface is exposed for patterning the dual damascene.
    Type: Grant
    Filed: December 6, 2000
    Date of Patent: March 16, 2004
    Assignee: Macronix International Co., Ltd.
    Inventor: Pei-Ren Jeng