Patents by Inventor Peter Altevogt
Peter Altevogt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11557335Abstract: The disclosure relates to an initialization circuit for initializing memory cells of a memory array including a common bit line. Individual memory cells are coupled to the common bit line of the memory array via at least one pass element of the individual memory cells. The initialization circuit is operable for receiving a set of partition addresses specifying the partitions, i.e. the memory cells to be initialized. The initialization circuit is operable for successively initializing one cell of the partitions to be initialized and iteratively initializing the remaining memory cells of the partitions to be initialized. A number of memory cells initialized simultaneously in one iteration increases from one iteration to another iteration. Initializing a certain memory cell comprises activating the pass element of the cell so that the memory cell is connected to the bit line. Further aspects relate to methods for initializing memory cells and semiconductor circuits.Type: GrantFiled: July 7, 2020Date of Patent: January 17, 2023Assignee: International Business Machines CorporationInventors: Martin Bernhard Schmidt, Peter Altevogt, Wolfgang Gellerich, Juergen Pille, Harry Barowski
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Patent number: 11302378Abstract: The disclosure relates to an initialization circuit for initializing memory cells of a memory array. The individual memory cells are coupled to a common bit line of the memory array via at least one pass element of the individual memory cells. Each individual memory cell comprises a charge-based storage element including a capacitance. The initialization circuit activates the pass elements of a plurality of the memory cells to be initialized such that the capacitances of the plurality of memory cells are connected simultaneously to the common bit line. Further, aspects of the disclosure relate to a method for initializing memory cells and a semiconductor circuit.Type: GrantFiled: July 7, 2020Date of Patent: April 12, 2022Assignee: International Business Machines CorporationInventors: Martin Bernhard Schmidt, Peter Altevogt, Wolfgang Gellerich, Juergen Pille, Christoph Raisch
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Publication number: 20220013159Abstract: The disclosure relates to an initialization circuit for initializing memory cells of a memory array. The individual memory cells are coupled to a common bit line of the memory array via at least one pass element of the individual memory cells. Each individual memory cell comprises a charge-based storage element including a capacitance. The initialization circuit activates the pass elements of a plurality of the memory cells to be initialized such that the capacitances of the plurality of memory cells are connected simultaneously to the common bit line. Further, aspects of the disclosure relate to a method for initializing memory cells and a semiconductor circuit.Type: ApplicationFiled: July 7, 2020Publication date: January 13, 2022Inventors: Martin Bernhard Schmidt, Peter Altevogt, Wolfgang Gellerich, Juergen Pille, Christoph Raisch
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Publication number: 20220013166Abstract: The disclosure relates to an initialization circuit for initializing memory cells of a memory array including a common bit line. Individual memory cells are coupled to the common bit line of the memory array via at least one pass element of the individual memory cells. The initialization circuit is operable for receiving a set of partition addresses specifying the partitions, i.e. the memory cells to be initialized. The initialization circuit is operable for successively initializing one cell of the partitions to be initialized and iteratively initializing the remaining memory cells of the partitions to be initialized. A number of memory cells initialized simultaneously in one iteration increases from one iteration to another iteration. Initializing a certain memory cell comprises activating the pass element of the cell so that the memory cell is connected to the bit line. Further aspects relate to methods for initializing memory cells and semiconductor circuits.Type: ApplicationFiled: July 7, 2020Publication date: January 13, 2022Inventors: Martin Bernhard Schmidt, Peter Altevogt, Wolfgang Gellerich, Juergen Pille, Harry Barowski
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Patent number: 10902348Abstract: Embodiments of the invention include a computer-implemented method of processor branch prediction. This method aims at training a machine-learning model of processor branch behavior while a processing unit executes computer instructions. Such instructions include branch instructions, load instructions and store instructions. The load instructions and the store instructions cause a control unit of the processing unit to load data from a memory into processor registers and store data from the processor registers to the memory, respectively. Basically, the training of the model involves, for each of N branch instructions (N>2) encountered whilst the processing unit executes said branch instructions: identifying a next branch instruction; and feeding the machine-learning model with carefully chosen inputs.Type: GrantFiled: May 19, 2017Date of Patent: January 26, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Peter Altevogt, Andreea Anghel, Gero Dittmann, Cedric Lichtenau, Thomas Pflueger
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Patent number: 10901745Abstract: A processor unit for processing storage instructions. The processor unit comprises a detection logic unit configured to identify at least two storage instructions for moving addressable words between registers of the processor unit and neighboring storage locations. The processor unit further comprises a combination unit configured to combine the identified instructions into a single combined instruction; and a data movement unit configured to move the words using the combined instruction.Type: GrantFiled: July 10, 2018Date of Patent: January 26, 2021Assignee: International Business Machines CorporationInventors: Cedric Lichtenau, Peter Altevogt, Thomas Pflueger
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Patent number: 10901908Abstract: The present disclosure relates to storing data in a computer system. The computer system comprising a main memory coupled to a processor and a cache hierarchy. The main memory comprises a predefined bit pattern replacing existing data of the main memory. Aspects include storing the predefined bit pattern into a reference storage of the computer system. At least one bit in a cache directory entry of a first cache line of the cache hierarchy can be set. Upon receiving a request to read the content of the first cache line, the request can be redirected to the predefined bit pattern in the reference storage based on the value of the set bit of the first cache line.Type: GrantFiled: January 16, 2019Date of Patent: January 26, 2021Assignee: International Business Machines CorporationInventors: Wolfgang Gellerich, Peter Altevogt, Martin Bernhard Schmidt, Martin Schwidefsky
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Patent number: 10901651Abstract: Embodiments of memory block erasure are described herein. An aspect includes determining an initial word line set consisting of a single word line. Another aspect includes activating the single word line such that a first memory cell that is connected to the single word line is erased by the activation. Another aspect includes determining a first word line set consisting of the single word line and one additional word line, and wherein the one additional word line corresponds to a second memory cell have a maximum distance from the first memory cell along a bit line that includes the first memory cell and the second memory cell. Another aspect includes activating the first word line set, such that a respective memory cell that is connected to each of the first word line set is erased by the activation.Type: GrantFiled: January 3, 2020Date of Patent: January 26, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Martin B. Schmidt, Peter Altevogt, Wolfgang Gellerich, Juergen Pille
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Patent number: 10896386Abstract: Embodiments of the invention include a computer-implemented method of processor branch prediction. This method aims at training a machine-learning model of processor branch behavior while a processing unit executes computer instructions. Such instructions include branch instructions, load instructions and store instructions. The load instructions and the store instructions cause a control unit of the processing unit to load data from a memory into processor registers and store data from the processor registers to the memory, respectively. Basically, the training of the model involves, for each of N branch instructions (N>2) encountered whilst the processing unit executes said branch instructions: identifying a next branch instruction; and feeding the machine-learning model with carefully chosen inputs.Type: GrantFiled: November 3, 2017Date of Patent: January 19, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Peter Altevogt, Andreea Anghel, Gero Dittmann, Cedric Lichtenau, Thomas Pflueger
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Patent number: 10754773Abstract: A method for dynamically selecting a size of a memory access may be provided. The method comprises accessing blocks having a variable number of consecutive cache lines, maintaining a vector with entries of past utilizations for each block size, and adapting said block size before a next access to the blocks.Type: GrantFiled: October 11, 2017Date of Patent: August 25, 2020Assignee: International Business Machines CorporationInventors: Andreea Anghel, Cedric Lichtenau, Gero Dittmann, Peter Altevogt, Thomas Pflueger
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Publication number: 20200226068Abstract: The present disclosure relates to storing data in a computer system. The computer system comprising a main memory coupled to a processor and a cache hierarchy. The main memory comprises a predefined bit pattern replacing existing data of the main memory. Aspects include storing the predefined bit pattern into a reference storage of the computer system. At least one bit in a cache directory entry of a first cache line of the cache hierarchy can be set. Upon receiving a request to read the content of the first cache line, the request can be redirected to the predefined bit pattern in the reference storage based on the value of the set bit of the first cache line.Type: ApplicationFiled: January 16, 2019Publication date: July 16, 2020Inventors: Wolfgang Gellerich, Peter Altevogt, Martin Bernhard Schmidt, Martin Schwidefsky
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Patent number: 10684861Abstract: The present disclosure relates to a method for instruction processing with a processor having multiple execution units. The processor includes a dependency cache containing instructions in association with respective execution unit indicators. The method includes: tracking the number of dependent instructions currently assigned to each execution unit of the processor respectively. In response to receiving an instruction of a dependency chain, the execution unit assigned to a previous instruction of the dependency chain on which depends the received instruction may be identified in the dependency cache. In case more than a predefined maximum number of dependent instructions of at least one dependency chain is currently assigned to the identified execution unit, another execution unit of the processor may be selected for scheduling the received instruction, otherwise the received instruction may be scheduled on the identified execution unit.Type: GrantFiled: September 25, 2017Date of Patent: June 16, 2020Assignee: International Business Machines CorporationInventors: Peter Altevogt, Cédric Lichtenau, Thomas Pflueger
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Publication number: 20200159440Abstract: Embodiments of memory block erasure are described herein. An aspect includes determining an initial word line set consisting of a single word line. Another aspect includes activating the single word line such that a first memory cell that is connected to the single word line is erased by the activation. Another aspect includes determining a first word line set consisting of the single word line and one additional word line, and wherein the one additional word line corresponds to a second memory cell have a maximum distance from the first memory cell along a bit line that includes the first memory cell and the second memory cell. Another aspect includes activating the first word line set, such that a respective memory cell that is connected to each of the first word line set is erased by the activation.Type: ApplicationFiled: January 3, 2020Publication date: May 21, 2020Inventors: Martin B. Schmidt, Peter Altevogt, Wolfgang Gellerich, Juergen Pille
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Patent number: 10649781Abstract: The present disclosure relates to a method for instruction processing with a processor having multiple execution units. The processor includes a dependency cache containing instructions in association with respective execution unit indicators. The method includes: tracking the number of dependent instructions currently assigned to each execution unit of the processor respectively. In response to receiving an instruction of a dependency chain, the execution unit assigned to a previous instruction of the dependency chain on which depends the received instruction may be identified in the dependency cache. In case more than a predefined maximum number of dependent instructions of at least one dependency chain is currently assigned to the identified execution unit, another execution unit of the processor may be selected for scheduling the received instruction, otherwise the received instruction may be scheduled on the identified execution unit.Type: GrantFiled: December 15, 2017Date of Patent: May 12, 2020Assignee: International Business Machines CorporationInventors: Peter Altevogt, Cédric Lichtenau, Thomas Pflueger
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Patent number: 10585619Abstract: Embodiments of memory block erasure are described herein. An aspect includes determining a first word line set consisting of a first plurality of word lines. Another aspect includes activating the first plurality of word lines, such that a respective memory cell that is connected to each of the first plurality of word lines is erased by the activation of the first plurality of word lines. Another aspect includes determining a second word line set, wherein the second word line set consists of the first word line set and a second plurality of word lines. Another aspect includes simultaneously activating the first plurality of word lines and the second plurality of word lines, such that a respective memory cell that is connected to each of the second plurality of word lines is erased by the activation of the first plurality of word lines and the second plurality of word lines.Type: GrantFiled: November 15, 2018Date of Patent: March 10, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Martin B. Schmidt, Peter Altevogt, Wolfgang Gellerich, Juergen Pille
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Publication number: 20200019407Abstract: A processor unit for processing storage instructions. The processor unit comprises a detection logic unit configured to identify at least two storage instructions for moving addressable words between registers of the processor unit and neighboring storage locations. The processor unit further comprises a combination unit configured to combine the identified instructions into a single combined instruction; and a data movement unit configured to move the words using the combined instruction.Type: ApplicationFiled: July 10, 2018Publication date: January 16, 2020Inventors: Cedric Lichtenau, Peter Altevogt, Thomas Pflueger
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Patent number: 10528354Abstract: A processor with multiple execution units for instruction processing is provided. The processor comprises an instruction decode and issue logic and a control logic for resolving register access conflicts between subsequent instructions and a dependency cache, which comprises a receiving logic for receiving an execution unit indicator indicative of the execution unit the instruction is planned to be executed on, a storing logic responsive to the receiving logic for storing the received execution unit indicator, and a retrieving logic responsive to a request from the instruction decode and issue logic for providing the stored execution unit indicator for an instruction. The instruction decode and issue logic is adapted for requesting execution unit indicator for an instruction from the dependency cache and to assign the instruction to one respective of the execution units dependent on the execution unit indicator received from the dependency cache.Type: GrantFiled: March 10, 2016Date of Patent: January 7, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Peter Altevogt, Cedric Lichtenau, Thomas Pflueger
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Publication number: 20190332525Abstract: A method of prefetching data is provided including monitoring sequences of memory addresses of data being accessed by a system, whereby sequences of m+1 memory addresses each are continually identified; and for each identified sequence: converting, upon identifying said each sequence, memory addresses of said each sequence into m relative addresses, whereby each of the m relative addresses is relative to a previous memory address in said each sequence, so as to obtain an auxiliary sequence of m relative addresses; upon converting said memory addresses, feeding said auxiliary sequence of m relative addresses as input to a trained machine learning model for it to predict p relative addresses of next memory accesses by the system, where p?1; and prefetching data at memory locations associated with one or more memory addresses that respectively correspond to one or more of the p relative addresses predicted.Type: ApplicationFiled: April 27, 2018Publication date: October 31, 2019Inventors: Andreea Anghel, Peter Altevogt, Gero Dittmann, Cedric Lichtenau
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Patent number: 10437718Abstract: A method of prefetching data is provided including monitoring sequences of memory addresses of data being accessed by a system, whereby sequences of m+1 memory addresses each are continually identified; and for each identified sequence: converting, upon identifying said each sequence, memory addresses of said each sequence into m relative addresses, whereby each of the m relative addresses is relative to a previous memory address in said each sequence, so as to obtain an auxiliary sequence of m relative addresses; upon converting said memory addresses, feeding said auxiliary sequence of m relative addresses as input to a trained machine learning model for it to predict p relative addresses of next memory accesses by the system, where p?1; and prefetching data at memory locations associated with one or more memory addresses that respectively correspond to one or more of the p relative addresses predicted.Type: GrantFiled: April 27, 2018Date of Patent: October 8, 2019Assignee: International Business Machines CorporationInventors: Andreea Anghel, Peter Altevogt, Gero Dittmann, Cedric Lichtenau
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Patent number: 10400037Abstract: The present disclosure relates to a binding molecule binding to L1, which is capable of binding to the same L1 epitope recognized by the monoclonal antibody L1-OV52.24, and/or which competes with the monoclonal antibody L1-OV52.24 for binding to L1, wherein the variable part of the light chain of L1-OV52.24 comprises the sequence according to SEQ ID No: 1 or wherein the light chain is encoded by SEQ ID No: 3, and wherein the variable part of the heavy chain of L1-OV52.24 comprises the sequence according to SEQ ID No: 2 or wherein the heavy chain is encoded by SEQ ID No: 4, nucleic acids encoding the binding molecules, uses thereof and pharmaceutical compositions comprising the binding molecules.Type: GrantFiled: September 28, 2015Date of Patent: September 3, 2019Assignee: DEUTSCHES KREBSFORSCHUNGSZENTRUM STIFTUNG DES ÖFFENTLICHEN RECHTSInventors: Peter Altevogt, Sandra Lüttgau, Gerhard Moldenhauer, John Hazin