Patents by Inventor Peter Anthony Franaszek

Peter Anthony Franaszek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8122216
    Abstract: Computer memory management systems and methods are provided in which data block buffering and priority scheduling protocols are utilized in compressed memory systems to mask the latency associated with memory reorganization work following access to compressed main memory. In particular, data block buffers and priority scheduling protocols are implemented to delay and prioritize memory reorganization work to allow resources to be used for serving new memory access requests and other high priority commands.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: February 21, 2012
    Assignee: International Business Machines Corporation
    Inventors: David Michael Daly, Peter Anthony Franaszek, Michael Ignatowski, Luis Alfonso Lastras-Montano, Michael Raymond Trombley
  • Patent number: 7962700
    Abstract: Compressed memory systems are provided to reduce latency associated with accessing compressed memory using stratified compressed memory architectures and memory organization protocols in which a region of compressed main memory is allocated as a direct access memory (DAM) region for storing uncompressed data items. The uncompressed data items in the DAM region can be directly accessed, speculatively, to serve access requests to main memory, requiring access to compressed memory in the event of a DAM miss.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: June 14, 2011
    Assignee: International Business Machines Corporation
    Inventors: Peter Anthony Franaszek, Luis Alfonso Lastras-Montano, Robert Brett Tremaine
  • Publication number: 20080059728
    Abstract: Computer memory management systems and methods are provided in which data block buffering and priority scheduling protocols are utilized in compressed memory systems to mask the latency associated with memory reorganization work following access to compressed main memory. In particular, data block buffers and priority scheduling protocols are implemented to delay and prioritize memory reorganization work to allow resources to be used for serving new memory access requests and other high priority commands.
    Type: Application
    Filed: September 6, 2006
    Publication date: March 6, 2008
    Inventors: David Michael Daly, Peter Anthony Franaszek, Michael Ignatowski, Luis Alfonso Lastras-Montano, Michael Raymond Trombley
  • Publication number: 20080055323
    Abstract: Compressed memory systems are provided to reduce latency associated with accessing compressed memory using stratified compressed memory architectures and memory organization protocols in which a region of compressed main memory is allocated as a direct access memory (DAM) region for storing uncompressed data items. The uncompressed data items in the DAM region can be directly accessed, speculatively, to serve access requests to main memory, requiring access to compressed memory in the event of a DAM miss.
    Type: Application
    Filed: September 6, 2006
    Publication date: March 6, 2008
    Inventors: Peter Anthony Franaszek, Luis Alfonso Lastras-Montano, Robert Brett Tremaine
  • Patent number: 7024512
    Abstract: An improved method, system, and a computer program storage device (e.g., including software embodied on a magnetic, electrical, optical, or other storage device) for management of compressed main memory allocation and utilization which can avoid system abends or inefficient operation that would otherwise result. One feature reduces (and ultimately eliminates) all unessential processing as the amount of available storage decreases to a point low enough to threaten a system abend. In another example, the amount of current memory usage is determined as well as one or more of: an estimate of an amount of allocated but unused memory; a determination of the amount of memory required for outstanding I/O requests. The compressed memory is managed as a function of the current memory usage and one or more of the other measured or estimated quantities.
    Type: Grant
    Filed: February 10, 1998
    Date of Patent: April 4, 2006
    Assignee: International Business Machines Corporation
    Inventors: Peter Anthony Franaszek, Philip Heidelberger
  • Patent number: 6804754
    Abstract: Memory is managed by controlling the expansion of memory contents, especially in those computing environments in which the memory contents are compressed. Control is provided by imposing some restrictions to memory references outside a specified subset of the memory contents, and by controlling the transfer of items into the subset. In one example, the transfer of items into the subset is based on a function of parameters, including an estimate of the amount of free space in the memory.
    Type: Grant
    Filed: May 21, 1997
    Date of Patent: October 12, 2004
    Assignee: International Business Machines Corporation
    Inventors: Peter Anthony Franaszek, Michel Henri Theodore Hack, Charles Otto Schulz, Thomas Basil Smith, III
  • Patent number: 6240419
    Abstract: Variable-length data, comprising of compressed pages, is stored in a memory so that access to any sub-page or line within a page may be started given a single address corresponding to the location of a fixed-length block within the memory.
    Type: Grant
    Filed: October 8, 1998
    Date of Patent: May 29, 2001
    Assignee: International Business Machines Corporation
    Inventor: Peter Anthony Franaszek
  • Patent number: 6215412
    Abstract: A new asynchronous approach used to quickly and dynamically switch input port connections to output port connections and to resolve contention. The switch is self-routing in two cycle times at the same high speed serial rate that data is transferred through the switch. The normal mode of the switch requires absolutely no synchronization amongst any of the input and output ports which interface to the switch. The switch is void of centrally controlled clocking and any data buffering. Data traverses the switch only encountering three gate delays—on-chip receiver, mux, and off-chip driver. Contention is detected and resolved on chip, and yet the logic implementation is extremely simple and low in gate count, so the switch design is never gate limited. The protocol requires several parallel data lines plus two or three control lines.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: April 10, 2001
    Assignee: International Business Machines Corporation
    Inventors: Peter Anthony Franaszek, Christos John Georgiou, Robert Francis Lusch, Joseph Michael Mosley, Howard Thomas Olnowich
  • Patent number: 5870036
    Abstract: A system and method for compressing and decompressing data using a plurality of data compression mechanisms. Representative samples of each block of data are tested to select an appropriate one of the data compression mechanisms to apply to the block. The block is then compressed using the selected one of the mechanisms and the compressed block is provided with an identifier of the selected mechanism. For decompression, the identifier is examined to select an appropriate one of the data decompression mechanisms to apply to the block. The block is then decompressed using the selected one of the mechanisms.
    Type: Grant
    Filed: February 24, 1995
    Date of Patent: February 9, 1999
    Assignee: International Business Machines Corporation
    Inventors: Peter Anthony Franaszek, John Timothy Robinson, Joy Aloysius Thomas
  • Patent number: 5864859
    Abstract: Variable-length data, comprising compressed pages, is stored in a memory so that access to any sub-page or line within a page can be started given a single address corresponding to the location of a fixed-length block within the memory.
    Type: Grant
    Filed: February 20, 1996
    Date of Patent: January 26, 1999
    Assignee: International Business Machines Corporation
    Inventor: Peter Anthony Franaszek
  • Patent number: 5860103
    Abstract: Minimal random disk write latency is achieved by limiting the number of logical address blocks that can be serviced by a disk to less that the actual number of physically addressable blocks of the system and having a disk controller dynamically map logical data blocks to physical disk blocks in such a fashion that each logical write can take place to any free location, where the free location can be chosen in any track of the current cylinder.
    Type: Grant
    Filed: June 16, 1997
    Date of Patent: January 12, 1999
    Assignee: International Business Machines Corporation
    Inventors: Peter Anthony Franaszek, John Timothy Robinson
  • Patent number: 5761536
    Abstract: A system and method for storing variable length objects such that memory fragmentation is reduced, while avoiding the need for memory reorganization. A remainder of a variable length object may be assigned to share a fixed-size block of storage with a remainder from another variable length object (two such remainders which share a block are referred to as roommates) on a best fit or first fit basis. One remainder is stored at one end of the block, while the other remainder is stored at the other end of the block. The variable length objects which are to share a block of storage are selected from the same cohort. Thus, there is some association between the objects. This association may be that the objects are from the same page or are in some linear order spanning multiple pages, as examples. Information regarding the variable length objects of a cohort, such as whether an object has a roommate, is stored in memory.
    Type: Grant
    Filed: August 21, 1996
    Date of Patent: June 2, 1998
    Assignee: International Business Machines Corporation
    Inventor: Peter Anthony Franaszek
  • Patent number: 5729228
    Abstract: A method and apparatus for compressing a block of data using a shared dictionary. Data to be compressed is divided into subblocks which are each provided to a respective compressor in a plurality of compressors. The compressors cooperatively construct a dynamic compression dictionary and compress the subblocks in parallel using the dictionary. Compressed subblocks output by the compressors are concatenated to form a compressed block.
    Type: Grant
    Filed: July 6, 1995
    Date of Patent: March 17, 1998
    Assignee: International Business Machines Corp.
    Inventors: Peter Anthony Franaszek, John Timothy Robinson, Joy Aloysius Thomas
  • Patent number: 5708793
    Abstract: Minimal random disk write latency is achieved by limiting the number of logical address blocks that can be serviced by a disk to less that the actual number of physically addressable blocks of the system and having a disk controller dynamically map logical data blocks to physical disk blocks in such a fashion that each logical write can take place to any free location, where the free location can be chosen in any track of the current cylinder.
    Type: Grant
    Filed: March 31, 1995
    Date of Patent: January 13, 1998
    Assignee: International Business Machines Corporation
    Inventors: Peter Anthony Franaszek, John Timothy Robinson
  • Patent number: 5654695
    Abstract: A multi-stage architecture for providing a single switching component in multiplicity to create a single network capable of performing a multiplicity of functions. One function of the disclosed network is to circumvent the traditional blocking problems in multi-stage networks by implementing ALTERNATE PATHS between devices within the same network. This permits a non-blocked path between 2 devices to be found by rearrangeability--the act of trying or searching different alternate paths until a non-blocked connection is established. A second network function permits a special high priority mode of transfer which will guarantee that the connection will be made to an idle device as rapidly as possible.
    Type: Grant
    Filed: February 23, 1996
    Date of Patent: August 5, 1997
    Assignee: International Business Machines Corporation
    Inventors: Howard Thomas Olnowich, Thomas Norman Barker, Peter Anthony Franaszek, Philip Heidelberger, Bharat Deep Rathi, Anujan Mangala Varma
  • Patent number: 4091242
    Abstract: A method of and apparatus for time compression and changing the readout speed of a delta modulation encoded audio signal. The encoded audio signal has portions selectively deleted therefrom in accordance with detected zero crossovers of the same sign which occur in a predetermined timing sequence. The encoded audio signal which has had portions selectively deleted therefrom is decoded, with the undeleted decoded portions being joined. The undeleted portions have the same gain factor where joined, thereby eliminating step transients.
    Type: Grant
    Filed: July 11, 1977
    Date of Patent: May 23, 1978
    Assignee: International Business Machines Corporation
    Inventors: Francis Paul Carrubba, Walter Edgar Daniels, Jr., Peter Anthony Franaszek
  • Patent number: 4052704
    Abstract: This memory management system provides an improved search logic for locating pages of data stored parallel-by-bit, serially-by-page in a shift register memory and for moving those pages to a position at the head of the file. Searching alternates between forward and reverse with a first direction change occurring when the head of the file occupies an input/output station in the memory and a second change occurring when the last of a plurality of pages identified for search at the first reversal position is found.The page numbers of three sought data pages are entered into three search registers and compared with the page number of each page as it is shifted into the input/output station of the memory. A page number is replaced when the page is found. Page numbers are marked with a binary one upon each direction change at the first position and with a binary zero at each replacement of a page number at other than that position.
    Type: Grant
    Filed: December 20, 1976
    Date of Patent: October 4, 1977
    Assignee: International Business Machines Corporation
    Inventor: Peter Anthony Franaszek
  • Patent number: 4028535
    Abstract: In a dynamic disc memory system, servo signal tracks and data tracks are adjacent. The servo track includes a signal having a predetermined frequency. With the system and method of this disclosure, the data recorded on the data track is translated to have a frequency null at the frequency of the servo signal track by translating apparatus to eliminate cross-talk at the servo frequency.
    Type: Grant
    Filed: June 11, 1976
    Date of Patent: June 7, 1977
    Assignee: International Business Machines Corporation
    Inventors: Peter Anthony Franaszek, David Allen Thompson