Patents by Inventor Peter C. Van Buskirk

Peter C. Van Buskirk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090205964
    Abstract: A sampling head, and/or an array including same for use in electrochemical deposition of various metal(s) on wafers or other substrates suitable for use in microelectronic devices or components thereof.
    Type: Application
    Filed: June 18, 2007
    Publication date: August 20, 2009
    Applicant: ADVANCED TECHNOLOGY MATERIALS, INC.
    Inventors: William Martin Holber, Mackenzie King, Peter C. Van Buskirk
  • Patent number: 7464192
    Abstract: A programmable serial interface is disclosed for use in a semiconductor circuit that supports a plurality of communication protocols. The programmable serial interface includes one or more shared hardware components that implement tasks and functions of a plurality of communication protocols, optional protocol specific hardware, a processor and memory. For each task or function required by a supported communication protocol, a determination is made as to which parts of the function will be implemented using shared hardware, protocol specific hardware or in software. The communication protocols to be supported are identified, and the functions performed in accordance with each of the supported protocols are analyzed to identify those functions suitable for common or shared hardware with other communication protocols. In addition, unique or time-critical functions are identified that must be implemented in hardware. Finally, any functions that are not implemented in hardware are implemented in software.
    Type: Grant
    Filed: September 10, 2002
    Date of Patent: December 9, 2008
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Philip C. Barnett, Andy Green, Peter C. Van Buskirk
  • Patent number: 7344589
    Abstract: A novel lead zirconium titanate (PZT) material having unique properties and application for PZT thin film capacitors and ferroelectric capacitor structures, e.g., FeRAMs, employing such thin film material. The PZT material is scalable, being dimensionally scalable, pulse length scalable and/or E-field scalable in character, and is useful for ferroelectric capacitors over a wide range of thicknesses, e.g., from about 20 nanometers to about 150 nanometers, and a range of lateral dimensions extending to as low as 0.15 ?m. Corresponding capacitor areas (i.e., lateral scaling) in a preferred embodiment are in the range of from about 104 to about 10?2 ?m2. The scalable PZT material of the invention may be formed by liquid delivery MOCVD, without PZT film modification techniques such as acceptor doping or use of film modifiers (e.g., Nb, Ta, La, Sr, Ca and the like).
    Type: Grant
    Filed: January 10, 2006
    Date of Patent: March 18, 2008
    Assignee: Advanced Technology Materials, Inc.
    Inventors: Peter C. Van Buskirk, Jeffrey F. Roeder, Steven M. Bilodeau, Michael W. Russell, Stephen T. Johnston, Daniel J. Vestyck, Thomas H. Baum
  • Patent number: 7012292
    Abstract: A method of preventing oxygen deficiency in a ferroelectric or high ? film material having a top electrode layer deposited thereon. Process conditions are employed that either enable the top electrode layer to be formed without oxygen abstraction from the ferroelectric or high ? film material in the vicinity and at the top surface thereof, or else provide the ferroelectric or high ? film material in the vicinity and at the top surface thereof with a surplus of oxygen. In the latter case, the deposition formation of the top electrode layer on the ferroelectric or high ? film material depletes the over-stoichiometric excess of the oxygen in the film material, to yield a device structure including an electrode on a film material having a proper stoichiometry, e.g., of PbZrTiO3.
    Type: Grant
    Filed: November 25, 1998
    Date of Patent: March 14, 2006
    Assignee: Advanced Technology Materials, Inc
    Inventors: Peter C. Van Buskirk, Steven M. Bilodeau, Stephen T. Johnston, Daniel J. Vestyck, Michael W. Russell
  • Patent number: 7005303
    Abstract: A low temperature CVD process for deposition of bismuth-containing ceramic thin films suitable for integration to fabricate ferroelectric memory devices. The bismuth-containing film can be formed using a tris(?-diketonate) bismuth precursor. Films of amorphous SBT can be formed by CVD and then ferroannealed to produce films with Aurivillius phase composition having superior ferroelectric properties suitable for manufacturing high density FRAMs.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: February 28, 2006
    Assignee: Advanced Technology Materials, Inc.
    Inventors: Frank S. Hintermaier, Christine Dehm, Wolfgang Hoenlein, Peter C. Van Buskirk, Jeffrey F. Roeder, Bryan C. Hendrix, Thomas H. Baum, Debra A. Desrochers
  • Patent number: 6984417
    Abstract: A novel lead zirconium titanate (PZT) material having unique properties and application for PZT thin film capacitors and ferroelectric capacitor structures, e.g., FeRAMs, employing such thin film material. The PZT material is scalable, being dimensionally scalable, pulse length scalable and/or E-field scalable in character, and is useful for ferroelectric capacitors over a wide range of thicknesses, e.g., from about 20 nanometers to about 150 nanometers, and a range of lateral dimensions extending to as low as 0.15 ?m. Corresponding capacitor areas (i.e., lateral scaling) in a preferred embodiment are in the range of from about 104 to about 10?2 ?m2. The scalable PZT material of the invention may be formed by liquid delivery MOCVD, without PZT film modification techniques such as acceptor doping or use of film modifiers (e.g., Nb, Ta, La, Sr, Ca and the like).
    Type: Grant
    Filed: August 13, 2001
    Date of Patent: January 10, 2006
    Assignee: Advanced Technology Materials, Inc.
    Inventors: Peter C. Van Buskirk, Jeffrey F. Roeder, Steven M. Bilodeau, Michael W. Russell, Stephen T. Johnston, Daniel J. Vestyck, Thomas H. Baum
  • Patent number: 6846424
    Abstract: A process for removing and/or dry etching noble metal-based material structures, e.g., iridium for electrode formation for a microelectronic device. Etch species are provided by plasma formation involving energization of one or more halogenated organic and/or inorganic substance, and the etchant medium including such etch species and oxidizing gas is contacted with the noble metal-based material under etching conditions. The plasma formation and the contacting of the plasma with the noble metal-based material can be carried out in a downstream microwave processing system to provide processing suitable for high-rate fabrication of microelectronic devices and precursor structures in which the noble metal forms an electrode, or other conductive element or feature of the product article.
    Type: Grant
    Filed: June 5, 2001
    Date of Patent: January 25, 2005
    Assignee: Advanced Technology Materials, Inc.
    Inventors: Thomas H. Baum, Phillip Chen, Frank DiMeo, Jr., Peter C. Van Buskirk, Peter S. Kirlin
  • Publication number: 20040209384
    Abstract: A low temperature CVD process for deposition of bismuth-containing ceramic thin films suitable for integration to fabricate ferroelectric memory devices. The bismuth-containing film can be formed using a tris(&bgr;-diketonate) bismuth precursor. Films of amorphous SBT can be formed by CVD and then ferroannealed to produce films with Aurivillius phase composition having superior ferroelectric properties suitable for manufacturing high density FRAMs.
    Type: Application
    Filed: April 30, 2004
    Publication date: October 21, 2004
    Inventors: Frank S. Hintermaier, Christine Dehm, Wolfgang Hoenlein, Peter C. Van Buskirk, Jeffrey F. Roeder, Bryan C. Hendrix, Thomas H. Baum, Debra A. Desrochers
  • Patent number: 6730523
    Abstract: A low temperature CVD process using a tris (&bgr;-diketonate) bismuth precursor for deposition of bismuth ceramic thin films suitable for integration to fabricate ferroelectric memory devices. Films of amorphous SBT can be formed by CVD and then ferroannealed to produce films with Aurivillius phase composition having superior ferroelectric properties suitable for manufacturing high density FRAMs.
    Type: Grant
    Filed: June 1, 2001
    Date of Patent: May 4, 2004
    Assignees: Advanced Technology Materials, Inc., Siemens Aktiengesellschaft
    Inventors: Frank S. Hintermaier, Christine Dehm, Wolfgang Hoenlein, Peter C. Van Buskirk, Jeffrey F. Roeder, Bryan C. Hendrix, Thomas H. Baum, Debra A. Desrochers
  • Patent number: 6709610
    Abstract: A method for removing from a microelectronic device structure a noble metal residue including at least one metal selected from the group consisting of platinum, palladium, iridium and rhodium, by contacting the microelectronic device structure with a cleaning gas including a reactive halide composition, e.g., XeF2, SF6, SiF4, Si2F6 or SiF3 and SiF2 radicals. The method may be carried out in a batch-cleaning mode, in which fresh charges of cleaning gas are successively introduced to a chamber containing the residue-bearing microelectronic device structure. Each charge is purged from the chamber after reaction with the residue, and the charging/purging is continued until the residue has been at least partially removed to a desired extent. Alternatively, the cleaning gas may be continuously flowed through the chamber containing the microelectronic device structure, until the noble metal residue has been sufficiently removed.
    Type: Grant
    Filed: January 24, 2001
    Date of Patent: March 23, 2004
    Assignee: Advanced Technology Materials, Inc.
    Inventors: Peter C. Van Buskirk, Frank DiMeo, Jr., Peter S. Kirlin, Thomas H. Baum
  • Patent number: 6699402
    Abstract: A chemical mechanical polishing (CMP) slurry composition for removing noble metal material from a substrate having the noble metal material deposited thereon, for example, a semiconductor device structure including thereon a layer of the noble metal material, e.g., iridium, patterned for use as an electrode. Such polishing slurry composition contains abrasive polishing particles, a bromide compound, a bromate compound for providing free bromine as an oxidizing agent in the composition, and an organic acid for mediating decomposition of the bromate compound in the composition. The CMP slurry composition of the invention is particularly effective for planarization and/or removal of noble metal(s) from the substrate, in applications such as the fabrication of ferroelectric or high permittivity capacitor devices.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: March 2, 2004
    Assignee: Advanced Technology Materials, Inc.
    Inventors: Michael W. Russell, Peter C. Van Buskirk, Jonathan J. Wolk, George E. Emond
  • Patent number: 6511856
    Abstract: A ferroelectric capacitor device structure, including a ferroelectric stack capacitor comprising a ferroelectric material capacitor element on a substrate containing buried transistor circuitry beneath an insulator layer having a via therein containing a conductive plug to the transistor circuitry, wherein E-fields are structurally confined to the ferroelectric capacitor material element.
    Type: Grant
    Filed: June 27, 2001
    Date of Patent: January 28, 2003
    Assignee: Advanced Technology Materials, Inc.
    Inventors: Peter C. Van Buskirk, Steven M. Bilodeau
  • Patent number: 6500489
    Abstract: Chemical vapor deposition is used to form a film of Bi oxide, Sr oxide, and Ta oxide on a heated substrate by decomposing the precursors of these oxides at the surface of the substrate. The precursor of Bi oxide is a Bi complex which includes at least one alkoxide group and is decomposed and deposited at a temperature lower than 450° C. The film of Bi, Sr, and Ta oxides obtained by low-temperature CVD is predominantly non-ferroelectric, but can be converted into a ferroelectric film by a subsequent heating process.
    Type: Grant
    Filed: December 9, 1998
    Date of Patent: December 31, 2002
    Assignees: Advanced Technology Materials, Inc., Infineon Technologies Corporation
    Inventors: Frank S. Hintermaier, Peter C. Van Buskirk, Jeffrey F. Roeder, Bryan C. Hendrix, Thomas H. Baum, Debra A. Desrochers
  • Publication number: 20020081849
    Abstract: A chemical mechanical polishing (CMP) slurry composition for removing noble metal material from a substrate having the noble metal material deposited thereon, for example, a semiconductor device structure including thereon a layer of the noble metal material, e.g., iridium, patterned for use as an electrode. Such polishing slurry composition contains abrasive polishing particles, a bromide compound, a bromate compound for providing free bromine as an oxidizing agent in the composition, and an organic acid for mediating decomposition of the bromate compound in the composition. The CMP slurry composition of the invention is particularly effective for planarization and/or removal of noble metal(s) from the substrate, in applications such as the fabrication of ferroelectric or high permittivity capacitor devices.
    Type: Application
    Filed: December 28, 2001
    Publication date: June 27, 2002
    Inventors: Michael W. Russell, Peter C. Van Buskirk, Jonathan J. Wolk, George T. Emond
  • Patent number: 6395194
    Abstract: A method of removing noble metal material from a substrate having the noble metal material deposited thereon, such as a semiconductor device structure including thereon a layer of the noble metal material, e.g., iridium, patterned for use as an electrode. The substrate is subjected to chemical mechanical polishing with a chemical mechanical polishing composition containing abrasive polishing particles and a halide-based oxidizing agent. The CMP composition and method of the invention provide efficient planarization and noble metal material removal from the substrate, in applications such as the fabrication of ferroelectric or high permittivity capacitor devices.
    Type: Grant
    Filed: December 18, 1998
    Date of Patent: May 28, 2002
    Assignees: Intersurface Dynamics Inc., Advanced Technology Materials, Inc.
    Inventors: Michael W. Russell, Peter C. Van Buskirk, Jonathan J. Wolk, George E. Emond
  • Patent number: 6346741
    Abstract: An integrated circuit structures formed by chemical mechanical polishing (CMP) process, which comprises a conductive pathway recessed in a dielectric substrate, wherein the conductive pathway comprises conductive transmission lines encapsulated in a transmission-enhancement material, and wherein the conductive pathway is filled sequentially by a first layer of the transmission-enhancement material followed by the conductive transmission line; a second layer of transmission-enhancement material encapsulating the conductive transmission line and contacting the first layer of the transmission-enhancement material, wherein the transmission-enhancement material is selected from the group consisting of high magnetic permeability material and high permittivity material. Such integrated circuit structure may comprise a device structure selected from the group consisting of capacitors, inductors, and resistors.
    Type: Grant
    Filed: November 25, 1998
    Date of Patent: February 12, 2002
    Assignee: Advanced Technology Materials, Inc.
    Inventors: Peter C. Van Buskirk, Michael W. Russell, Steven M. Bilodeau, Thomas H. Baum
  • Publication number: 20020014644
    Abstract: A novel lead zirconium titanate (PZT) material having unique properties and application for PZT thin film capacitors and ferroelectric capacitor structures, e.g., FeRAMs, employing such thin film material. The PZT material is scalable, being dimensionally scalable, pulse length scalable and/or E-field scalable in character, and is useful for ferroelectric capacitors over a wide range of thicknesses, e.g., from about 20 nanometers to about 150 nanometers, and a range of lateral dimensions extending to as low as 0.15 &mgr;m. Corresponding capacitor areas (i.e., lateral scaling) in a preferred embodiment are in the range of from about 104 to about 10−2 &mgr;m2. The scalable PZT material of the invention may be formed by liquid delivery MOCVD, without PZT film modification techniques such as acceptor doping or use of film modifiers (e.g., Nb, Ta, La, Sr, Ca and the like).
    Type: Application
    Filed: August 13, 2001
    Publication date: February 7, 2002
    Applicant: Advanced Technology Materials, Inc.
    Inventors: Peter C. Van Buskirk, Jeffrey F. Roeder, Steven M. Bilodeau, Michael W. Russell, Stephen T. Johnston, Daniel J. Vestyck, Thomas H. Baum
  • Publication number: 20020011463
    Abstract: A method for removing from a microelectronic device structure a noble metal residue including at least one metal selected from the group consisting of platinum, palladium, iridium and rhodium, by contacting the microelectronic device structure with a cleaning gas including a reactive halide composition, e.g., XeF2, SF6, SiF4, Si2F6 or SiF3 and SiF2 radicals. The method may be carried out in a batch-cleaning mode, in which fresh charges of cleaning gas are successively introduced to a chamber containing the residue-bearing microelectronic device structure. Each charge is purged from the chamber after reaction with the residue, and the charging/purging is continued until the residue has been at least partially removed to a desired extent. Alternatively, the cleaning gas may be continuously flowed through the chamber containing the microelectronic device structure, until the noble metal residue has been sufficiently removed.
    Type: Application
    Filed: January 24, 2001
    Publication date: January 31, 2002
    Applicant: Advanced Technology Materials, Inc.
    Inventors: Peter C. Van Buskirk, Frank DiMeo, Peter S. Kirlin, Thomas H. Baum
  • Patent number: 6342711
    Abstract: A ferroelectric capacitor device structure, including a ferroelectric stack capacitor comprising a ferroelectric material capacitor element on a substrate containing buried transistor circuitry beneath an insulator layer having a via therein containing a conductive plug to the transistor circuitry, wherein E-fields are structurally confined to the ferroelectric capacitor material element.
    Type: Grant
    Filed: March 8, 1999
    Date of Patent: January 29, 2002
    Assignee: Advanced Technology Materials, Inc.
    Inventors: Peter C. Van Buskirk, Steven M. Bilodeau
  • Publication number: 20010041374
    Abstract: A low temperature CVD process using a tris (&bgr;-diketonate) bismuth precursor for deposition of bismuth ceramic thin films suitable for integration to fabricate ferroelectric memory devices. Films of amorphous SBT can be formed by CVD and then ferroannealed to produce films with Aurivillius phase composition having superior ferroelectric properties suitable for manufacturing high density FRAMs.
    Type: Application
    Filed: June 1, 2001
    Publication date: November 15, 2001
    Applicant: Advanced Technology Materials, Inc.
    Inventors: Frank S. Hintermaier, Christine Dehm, Wolfgang Hoenlein, Peter C. Van Buskirk, Jeffrey F. Roeder, Bryan C. Hendrix, Thomas H. Baum, Debra A. Desrochers