Abstract: Presently most MPEG video decoders use 16 Mbit of external memory. This memory capacity is almost completely occupied by the video decoding process in case of 625 line/50 Hz systems. Also the communication speed to the external memory is rather high. In future decoders, additional functions will be added to the video decoder, a need for free memory space and communication bandwidth will come up soon. Memory bandwidth becomes available with the application of synchronous dynamic random access memories (SDRAM) although high memory bandwidths lead to high operating frequencies. In order to release some memory capacity, a modification in the video decoding process is proposed by which 1 up to 3 Mbit of memory capacity can be saved. This modification has no big impact on the memory communication bandwidth. In order to keep the speed requirements in the variable length decoding within practical limits, a 2 step video decoding approach is proposed.

Abstract: Conventional MPEG decoders require about 16 Mbits of external memory to contain the input buffer, the two usual reference frames, and the B-information. As proposed earlier, about 2,8 Mbit in memory capacity can be saved by omitting the storage of B-information. The system, provides a further exchange between memory capacity and internal processing, to effect MPEG decoding, with only one reference frame stored in memory. All B and P information required for the reconstruction of display information which cannot directly be retrieved from memory is decoded instantaneously. Three decoding sub-steps are provided, a first decoding sub-step for the macroblock parameters, a second decoding sub-step for the picture elements according to a decoding-on-the-fly principle, and a third decoding sub-step for updating of the earlier reference frame after decoding of a later reference frame.

Abstract: The invention relates to a memory device of the charge-coupled shift register type which is subdivided into four sections each of which has a storage capacity of, for example 208,800 bits and which can operate in different modes: parallel-in/parallel-out (as background video memory); 2.times.2 parallel-in, demultiplex/multiplex mode, for example for 100 Hz TV; scan mode; parallel-in-recirculation mode; "shortened" memory, for example for 525-line system, etcetera. Control is realized via a decoding and timing block in which a multi-bit control word is serially input and decoded. In a scan mode (for example, as a teletext memory), the memory sections are scanned one-by-one under the control of a separate scan register in which a scan bit (logic 1) is step-wise shifted until all sections have been read. Via a data output, the scan bit is transferred, for example to the scan register of a further memory device (via its serial data input) which is connected in series with the former memory device.

Abstract: In order that one clock signal generator in a digital video signal processing circuit comprising a line-coupled clock signal generator and using, for example one or more field memories is sufficient for writing and reading these memories and can still process a signal from a video recorder, the control loop of the clock signal generator uses a comb filter circuit which rapidly corrects regular variations in an output signal of a phase detector of the control loop, which variations are caused by the head drum of the video recorder, without having to adapt the proportioning of a conventional loop filter circuit.

Abstract: A movement-adaptive processing circuit for an interlaced video signal has a selection circuit (5) which passes on to its output (21) one of the three video signals applied to its inputs (3, 9, 11) and which signals substantially correspond to three position-sequential lines of two consecutive fields when this signal has an amplitude which is closest to the mean amplitude of these three video signals. The processing circuit may be used many types of circuits such as, for example, in line or field number conversion circuits, noise suppression circuits, DPCM decoding circuits, vertical contour correction circuits and still-picture display circuits of video record players.

Abstract: In a television circuit arrangement for field and line frequency doubling and picture part magnification (zooming), in order to obtain the frequency doubling, information is written, alternately, into two field memories (M1, M2) during a field period having line periods at a given writing speed (clock frequency fc), whereby the reading from the field memories takes place at twice the writing speed. For a picture part magnification to be carried out in a simple manner, a magnification control circuit (TG, S3, S4, S11, S12) having a clock signal change-over circuit (S3, S4) is provided, as a result of which during writing, a higher writing speed (clock frequency 2fc) than the said given writing speed (clock frequency fc) is used during a part of the field periods and of the line periods, which part is substantially inversely proportional to the ratio between the higher writing speed and the given writing speed.