Patents by Inventor Peter Hoh In

Peter Hoh In has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090265201
    Abstract: Provided are a method and apparatus for determining a security solution. The method and apparatus generate a security solution analysis model for analyzing effects on investment of security solution combinations consisting of several security solution candidates on the basis of integer programming (IP), standardize various constraints that have significant effects on security solution determination on the basis of IP, and apply the standardized constraints to the security solution analysis model, thereby determining a security solution combination having the smallest residual risk while satisfying the constraints as an optimum security solution combination. According to the method and apparatus, an optimum security solution combination that can minimize a residual risk while satisfying various constraints is rapidly and accurately determined. Thus, it is possible to support effective determination in information security investment.
    Type: Application
    Filed: April 20, 2009
    Publication date: October 22, 2009
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Min Sik KIM, Jung Gil PARK, Soon Jwa HONG, Peter Hoh In, Taek LEE
  • Patent number: 6548357
    Abstract: Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost.
    Type: Grant
    Filed: April 8, 2002
    Date of Patent: April 15, 2003
    Assignees: International Business Machines Corporation, Infineon Technologies AG
    Inventors: Mary E. Weybright, Gary Bronner, Richard A. Conti, Ramachandra Divakaruni, Jeffrey Peter Gambino, Peter Hoh, Uwe Schroeder
  • Patent number: 6486505
    Abstract: In one aspect, the present invention discloses a transistor device (see e.g., FIG. 3) that includes first and second source/drain regions 124a and 126 disposed in a semiconductor body 122 and separated by a channel region 128a. A dielectric layer 134a overlies the channel region 128a and a gate electrode 130a/132a overlies the dielectric layer 134a. In the preferred embodiment, the gate electrode includes a polysilicon layer 130a that extends a first lateral distance over the dielectric layer and a silicide layer 132a that extends a second lateral distance over the first polysilicon layer. In this example, the first lateral distance is greater than the second lateral distance.
    Type: Grant
    Filed: March 24, 2000
    Date of Patent: November 26, 2002
    Assignee: Infineon Technologies, AG
    Inventors: Thomas S. Rupp, Jeffrey P. Gambino, Peter Hoh, Senthil Srinivasan
  • Publication number: 20020111025
    Abstract: Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost.
    Type: Application
    Filed: April 8, 2002
    Publication date: August 15, 2002
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mary E. Weybright, Gary Bronner, Richard A. Conti, Ramachandra Divakaruni, Jeffrey Peter Gambino, Peter Hoh, Uwe Schroeder
  • Patent number: 6403423
    Abstract: Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made-smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost.
    Type: Grant
    Filed: November 15, 2000
    Date of Patent: June 11, 2002
    Assignee: International Business Machines Corporation
    Inventors: Mary E. Weybright, Gary Bronner, Richard A. Conti, Ramachandra Divakaruni, Jeffrey Peter Gambino, Peter Hoh, Uwe Schroeder
  • Patent number: 6228279
    Abstract: By providing a photoresist material with a protective polymer layer during the etching of an organic anti-reflective coating, undue damage to the photoresist material can be avoided during opening of the anti-reflective coating without the need for an oxidant. The preferred polymer chemistry system for producing such a result includes a fluorohydrocarbon-containing polymer mixture with a strong source of CF3, preferably C2F6. The etchant also includes a source of hydrogen selected from CH3F, C2HF5, or CH2F2, and a diluent selected from Ar, He or N2.
    Type: Grant
    Filed: September 17, 1998
    Date of Patent: May 8, 2001
    Assignee: International Business Machines Corporation
    Inventors: Michael Armacost, Peter Hoh, Richard S. Wise, Wendy Yan