Patents by Inventor Peter Johnson

Peter Johnson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7644490
    Abstract: A method of forming an actuator and a relay using a micro-electromechanical (MEMS)-based process is disclosed. The method first forms the lower sections of a square copper coil, and then forms an actuation member that includes a core section and a horizontally adjacent floating cantilever section. The core section, which lies directly over the lower coil sections, is electrically isolated from the lower coil sections. The method next forms the side and upper sections of the coil, along with first and second electrodes that are separated by a switch gap. The first electrode lies directly over an end of the core section, while the second electrode lies directly over an end of the floating cantilever section.
    Type: Grant
    Filed: May 25, 2007
    Date of Patent: January 12, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Trevor Niblock, Peter Johnson
  • Patent number: 7636434
    Abstract: When replacing an old exchange with a new one, one or more of a small unit (board or magazine) of the old exchange is removed at a time, and replaced by new equipment controlled through a different communications channel than the old equipment. This enables reuse of the existing MDF as well as the cabling from the MDF to the old exchange, which saves cost and also eliminates the need for a lot of changes to cabling documentation and support systems for handling cabling information. When upgrading as described, the new line boards can be designed to provide both voice and DSL services, or else can be made smaller or with higher capacity, so that extra space is freed up for placement of DSL equipment. The new equipment is installed in the same place as the old line board, or at least close enough to the corresponding cabling so that existing line connectors can be used.
    Type: Grant
    Filed: October 25, 2004
    Date of Patent: December 22, 2009
    Assignee: Telefonaktiebolaget L M Ericsson (Publ)
    Inventors: Magnus Lindgren, Stephen Doe, Peter Johnson
  • Patent number: 7633373
    Abstract: A thin film resistor is formed to have very accurately defined dimensions which, in turn, allow the resistive value of the resistor to be very accurately defined. The resistor is formed on spaced-apart conductive pads which, in turn, are electrically connected to conductive plugs that are spaced apart from the resistor.
    Type: Grant
    Filed: December 19, 2005
    Date of Patent: December 15, 2009
    Assignee: National Semiconductor Corporation
    Inventors: Peter Johnson, Joseph A. De Santis, Richard Wendell Foote, Jr.
  • Publication number: 20090256667
    Abstract: A scalable MEMS inductor is formed on the top surface of a semiconductor die. The MEMS inductor includes a plurality of magnetic lower laminations, a circular trace that lies over and spaced apart from the magnetic lower laminations, and a plurality of upper laminations that lie over and spaced apart from the circular trace.
    Type: Application
    Filed: April 9, 2008
    Publication date: October 15, 2009
    Inventors: Peter Smeys, Peter Johnson
  • Publication number: 20090256236
    Abstract: The bow in a wafer that results from fabricating a large number of MEMS devices on the top surface of the passivation layer of the wafer so that a MEMS device is formed over each die region is reduced by forming a stress relief layer between the passivation layer and the MEMS devices.
    Type: Application
    Filed: April 9, 2008
    Publication date: October 15, 2009
    Inventors: Peter Smeys, Peter Johnson
  • Patent number: 7584533
    Abstract: A damascene process is utilized to fabricate the segmented magnetic core elements of an integrated circuit inductor structure. The magnetic core is electroplated from a seed layer that is conformal with a permanent dielectric mold that results in sidewall plating defining an easy magnetic axis. The hard axis runs parallel to the longitudinal axis of the core and the inductor coils are orthogonal to the core's longitudinal axis. The magnetic field generated by the inductor coils is, therefore, parallel and self-aligned to the hard magnetic axis. The easy axis can be enhanced by electroplating in an applied magnetic field parallel to the easy axis.
    Type: Grant
    Filed: October 10, 2007
    Date of Patent: September 8, 2009
    Assignee: National Semiconductor Corporation
    Inventors: Peter Smeys, Peter Johnson, Andrei Papou
  • Publication number: 20090181473
    Abstract: A damascene process is utilized to fabricate the segmented magnetic core elements of an integrated circuit inductor structure. The magnetic core is electroplated from a seed layer that is conformal with a permanent dielectric mold that results in sidewall plating defining an easy magnetic axis. The hard axis runs parallel to the longitudinal axis of the core and the inductor coils are orthogonal to the core's longitudinal axis. The magnetic field generated by the inductor coils is, therefore, parallel and self-aligned to the hard magnetic axis. The easy axis is enhanced by electroplating in an applied magnetic field parallel to the easy axis.
    Type: Application
    Filed: November 21, 2008
    Publication date: July 16, 2009
    Inventors: Peter Smeys, Peter Johnson, Andrei Papou
  • Patent number: 7531824
    Abstract: An apparatus and method for fabricating high value inductors embedded on semiconductor integrated circuit. The apparatus and method involve forming a conductor on the semiconductor substrate. Once the conductor is formed, a polymer material is provided on the substrate surrounding the conductor. The polymer material contains a ferromagnetic material so that the permeability of the polymer is greater than one. In various embodiments, the ferromagnetic material may be any one of a number of different high permeable materials such as iron oxide, zinc, manganese, zirconium, samarium (SA), neodymium (NA), cobalt, nickel or a combination thereof.
    Type: Grant
    Filed: November 14, 2005
    Date of Patent: May 12, 2009
    Assignee: National Semiconductor Corporation
    Inventors: Peter Johnson, Peter J. Hopper, Kyuwoon Hwang, William French
  • Patent number: 7528012
    Abstract: An apparatus and method for a heat sink to dissipate the heat sourced by the encapsulated transistors in a SOI wafer. The apparatus includes a transistor formed in the active silicon layer of the wafer. The active surface is formed over an oxide layer and a bulk silicon layer. A heat sink is formed in the bulk silicon layer and configured to sink heat through the bulk silicon layer, to the back surface of the wafer. After the transistor is fabricated, the heat sink is formed by masking, patterning and etching the back surface of the wafer to form plugs in the bulk silicon layer. The plug extends through the thickness of the bulk layer to the oxide layer. Thereafter, the plug is filled with a thermally conductive material, such as a metal or DAG (thermally conductive paste). During operation, heat from the transistor is dissipated through the heat sink. In various embodiments of the invention, the plug hole is formed using either an anisotropic plasma or wet etch.
    Type: Grant
    Filed: August 22, 2006
    Date of Patent: May 5, 2009
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Iouri Mirgorodski, Vladislav Vashchenko, Peter Johnson
  • Publication number: 20090111381
    Abstract: A method and apparatus for utilizing a switched beam directional antenna in a wireless transmit/receive unit (WTRU) is disclosed. A wireless communication system includes a serving cell, a neighbor cell and a WTRU. The WTRU is configured to generate and steer a directional beam in a plurality of directions. Once the WTRU registers with the wireless communication system, the WTRU receives messages transmitted by the serving cell. The WTRU measures signal quality of messages received in each of a plurality of predetermined directions while steering the directional beam antenna. The WTRU selects a particular one of the directions having the best signal quality. As the WTRU constantly moves, the WTRU monitors signal quality in the selected direction, and switches to another direction when the signal quality in a current direction drops below a predetermined threshold.
    Type: Application
    Filed: December 1, 2008
    Publication date: April 30, 2009
    Applicant: INTERDIGITAL TECHNOLOGY CORPORATION
    Inventors: Kevin Peter Johnson, Ross L. Lintelman, Michael James Lynch, Gregg Arthur Charlton, Carl Wang, Kambiz Casey Zangi
  • Publication number: 20090094818
    Abstract: A damascene process is utilized to fabricate the segmented magnetic core elements of an integrated circuit inductor structure. The magnetic core is electroplated from a seed layer that is conformal with a permanent dielectric mold that results in sidewall plating defining an easy magnetic axis. The hard axis runs parallel to the longitudinal axis of the core and the inductor coils are orthogonal to the core's longitudinal axis. The magnetic field generated by the inductor coils is, therefore, parallel and self-aligned to the hard magnetic axis. The easy axis can be enhanced by electroplating in an applied magnetic field parallel to the easy axis.
    Type: Application
    Filed: October 10, 2007
    Publication date: April 16, 2009
    Inventors: Peter Smeys, Peter Johnson, Andrei Papou
  • Patent number: 7507589
    Abstract: A very, very low resistance micro-electromechanical system (MEMS) inductor, which provides resistance in the single-digit milliohm range, is formed by utilizing a single thick wide loop of metal formed around a magnetic core structure. The magnetic core structure, in turn, can utilize a laminated Ni—Fe structure that has an easy axis and a hard axis.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: March 24, 2009
    Assignee: National Semiconductor Corporation
    Inventors: Peter Johnson, Peter J. Hopper, Kyuwoon Hwang, Robert Drury
  • Publication number: 20090038142
    Abstract: The claimed invention pertains to methods of forming one or more inductors on a semiconductor substrate. In one embodiment, a method of forming an array of inductor core elements on a semiconductor substrate that includes integrated circuits is disclosed. A first set of spaced apart metallic core elements are formed over the substrate. Isolation sidewalls are then formed on side surfaces of the core elements. Afterward, a second set of metallic core elements are formed over the substrate. In some embodiments, at least one core element of the second set of core elements is positioned in a space between an associated adjacent pair of core elements from the first set of core elements. The first and second sets of core elements are substantially co-planar and interleaved such that only the isolation sidewalls separate adjacent core elements.
    Type: Application
    Filed: October 13, 2008
    Publication date: February 12, 2009
    Applicant: NATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Peter J. HOPPER, Peter JOHNSON, Peter SMEYS, Andrei PAPOU
  • Publication number: 20090040000
    Abstract: The claimed invention relates to arrangements of inductors and integrated circuit dice. One embodiment pertains to an integrated circuit die that has an inductor formed thereon. The inductor includes an inductor winding having a winding input and a winding output. The inductor also comprises an inductor core array having at least first and second sets of inductor core elements that are magnetically coupled with the inductor winding. Each inductor core element in the first set of inductor core elements is formed from a first metallic material. Each inductor core element in the second set of inductor core elements is formed from a second metallic material that has a different magnetic coercivity than the first magnetic material. The inductor further comprises a set of spacers that electrically isolate the inductor core elements. Some embodiments involve multiple inductor windings and/or multiple inductor core elements that magnetically interact in various ways.
    Type: Application
    Filed: October 13, 2008
    Publication date: February 12, 2009
    Applicant: NATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Peter J. Hopper, Peter Johnson, Peter Smeys, Andrei Papou
  • Patent number: 7468899
    Abstract: An apparatus and method for wafer level fabrication of high value inductors directly on top of semiconductor integrated circuits is disclosed. The integrated circuit includes a plurality of regulator circuits, each of the regulator circuits having an input node configured to receive a plurality of pulsed input signals having a predetermined duty cycle and a plurality of inductor windings associated with each of the plurality of regulator circuits respectively. The integrated circuit also includes a core array having a plurality of core elements. The plurality of core elements are positioned adjacent to and magnetically coupled with one or more of the plurality of inductor windings. An output node is electrically coupled to the plurality of inductor windings. The output signal at the output node is the sum of the instantaneous voltage on each of the inductor windings associated with the plurality of regulator circuits respectively.
    Type: Grant
    Filed: January 9, 2007
    Date of Patent: December 23, 2008
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Peter Johnson, Peter Smeys, Andrei Papou
  • Patent number: 7464459
    Abstract: A method of forming an actuator and a relay using a micro-electromechanical (MEMS)-based process is disclosed. The method first forms the lower sections of a square copper coil, and then forms a magnetic core member. The magnetic core member, which lies directly over the lower coil sections, is electrically isolated from the lower coil sections. The method next forms the side and upper sections of the coil, followed by the formation of an overlying cantilevered magnetic flexible member. Switch electrodes, which are separated by a switch gap, can be formed on the magnetic core member and the magnetic flexible member, and closed and opened in response to the electromagnetic field that arises in response to a current in the coil.
    Type: Grant
    Filed: May 25, 2007
    Date of Patent: December 16, 2008
    Assignee: National Semiconductor Corporation
    Inventors: Trevor Niblock, Peter Johnson
  • Patent number: 7463131
    Abstract: An on-chip inductor structure includes top and bottom metal plates that are formed to surround a conductor coil formed between the top and bottom plates, but is separated therefrom by intervening dielectric material. The top and bottom plates are preferably formed from a ferromagnetic alloy, e.g. Permalloy, and are subdivided into a plurality of space-apart segments, thereby reducing eddy currents. The number of segments is optimized based upon the process technology utilized to fabricate the structure. Preferably, a finite gap is formed between the top plate and the bottom plate, the height of the gap being chosen to adjust the total inductance of the structure.
    Type: Grant
    Filed: April 21, 2005
    Date of Patent: December 9, 2008
    Assignee: National Semiconductor Corporation
    Inventors: Kyuwoon Hwang, Peter J. Hopper, Robert Drury, Peter Johnson
  • Patent number: 7460834
    Abstract: A method and apparatus for utilizing a switched beam directional antenna in a wireless transmit/receive unit (WTRU) is disclosed. A wireless communication system includes a serving cell, a neighbor cell and a WTRU. The WTRU is configured to generate and steer a directional beam in a plurality of directions. Once the WTRU registers with the wireless communication system, the WTRU receives messages transmitted by the serving cell. The WTRU measures signal quality of messages received in each of a plurality of predetermined directions while steering the directional beam antenna. The WTRU selects a particular one of the directions having the best signal quality. As the WTRU constantly moves, the WTRU monitors signal quality in the selected direction, and switches to another direction when the signal quality in a current direction drops below a predetermined threshold.
    Type: Grant
    Filed: November 24, 2004
    Date of Patent: December 2, 2008
    Assignee: InterDigital Technology Corporation
    Inventors: Kevin Peter Johnson, Ross L. Lintelman, Michael James Lynch, Gregg Arthur Charlton, Carl Wang, Kambiz Casey Zangi
  • Patent number: 7435628
    Abstract: A vertical MOS transistor has a source region, a channel region, and a drain region that are vertically stacked, and a trench that extends from the top surface of the drain region through the drain region, the channel region, and partially into the source region. The vertical MOS transistor also has an insulation layer that lines the trench, and a conductive gate region that contacts the insulation layer to fill up the trench.
    Type: Grant
    Filed: July 27, 2007
    Date of Patent: October 14, 2008
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Yuri Mirgorodski, Vladislav Vashchenko, Peter Johnson
  • Patent number: D590458
    Type: Grant
    Filed: December 21, 2004
    Date of Patent: April 14, 2009
    Assignee: Race Face Components, Inc.
    Inventors: Bryn Peter Johnson, Sven Sturm