Patents by Inventor Peter Micah Sandvik

Peter Micah Sandvik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130328064
    Abstract: A method of forming a silicon carbide transient voltage suppressor (TVS) assembly and a system for a transient voltage suppressor (TVS) assembly are provided. The TVS assembly includes a semiconductor die in a mesa structure that includes a first layer of a first wide band gap semiconductor having a conductivity of a first polarity, a second layer of the first or a second wide band gap semiconductor having a conductivity of a second polarity coupled in electrical contact with the first layer wherein the second polarity is different than the first polarity. The TVS assembly also includes a third layer of the first, the second, or a third wide band gap semiconductor having a conductivity of the first polarity coupled in electrical contact with the second layer. The layer having a conductivity of the second polarity is lightly doped relative to the layers having a conductivity of the first polarity.
    Type: Application
    Filed: August 15, 2013
    Publication date: December 12, 2013
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Avinash Srikrishnan Kashyap, David Mulford Shaddock, Emad Andarawis Andarawis, Peter Micah Sandvik, Stephen Daley Arthur, Vinayak Tilak
  • Patent number: 8530902
    Abstract: A method of forming a silicon carbide transient voltage suppressor (TVS) assembly and a system for a transient voltage suppressor (TVS) assembly are provided. The TVS assembly includes a semiconductor die in a mesa structure that includes a first layer of a first wide band gap semiconductor having a conductivity of a first polarity, a second layer of the first or a second wide band gap semiconductor having a conductivity of a second polarity coupled in electrical contact with the first layer wherein the second polarity is different than the first polarity. The TVS assembly also includes a third layer of the first, the second, or a third wide band gap semiconductor having a conductivity of the first polarity coupled in electrical contact with the second layer. The layer having a conductivity of the second polarity is lightly doped relative to the layers having a conductivity of the first polarity.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: September 10, 2013
    Assignee: General Electric Company
    Inventors: Avinash Srikrishnan Kashyap, David Mulford Shaddock, Emad Andarawis Andarawis, Peter Micah Sandvik, Stephen Daley Arthur, Vinayak Tilak
  • Patent number: 8505303
    Abstract: The present invention discloses a combustor system and method of measuring impurities in the combustion system. The combustion system includes an up-stream fuel injection point; a down-stream turbine combustor; a flame zone in the turbine combustor comprising a plurality of axial sub-zones; an optical port assembly configured to obtain a non-axial, direct, optical view of at least one of the plurality of axial sub-zones, and an impurity detection system in optical communication with the optical port assembly.
    Type: Grant
    Filed: December 11, 2009
    Date of Patent: August 13, 2013
    Assignee: General Electric Company
    Inventors: Peter Micah Sandvik, Richard Dale Slates, Alexey Vasily Vert, Samer Aljabari
  • Patent number: 8507986
    Abstract: In one embodiment, the invention comprises a MOSFET comprising individual MOSFET cells. Each cell comprises a U-shaped well (P type) and two parallel sources (N type) formed within the well. A Number of source rungs (doped N) connect sources at multiple locations. Regions between two rungs comprise a body (P type). These features are formed on an N-type epitaxial layer, which is formed on an N-type substrate. A contact extends across and contacts a number of source rungs and bodies. Gate oxide and a gate contact overlie a leg of a first well and a leg of a second adjacent well, inverting the conductivity responsive to a gate voltage. A MOSFET comprises a plurality of these cells to attain a desired low channel resistance. The cell regions are formed using self-alignment techniques at several states of the fabrication process.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: August 13, 2013
    Assignee: General Electric Company
    Inventors: Stephen Daley Arthur, Kevin Sean Matocha, Peter Micah Sandvik, Zachary Matthew Stum, Peter Almren Losee, James Jay McMahon
  • Publication number: 20130105816
    Abstract: A method of forming a silicon carbide transient voltage suppressor (TVS) assembly and a system for a transient voltage suppressor (TVS) assembly are provided. The TVS assembly includes a semiconductor die in a mesa structure that includes a first layer of a first wide band gap semiconductor having a conductivity of a first polarity, a second layer of the first or a second wide band gap semiconductor having a conductivity of a second polarity coupled in electrical contact with the first layer wherein the second polarity is different than the first polarity. The TVS assembly also includes a third layer of the first, the second, or a third wide band gap semiconductor having a conductivity of the first polarity coupled in electrical contact with the second layer. The layer having a conductivity of the second polarity is lightly doped relative to the layers having a conductivity of the first polarity.
    Type: Application
    Filed: October 26, 2011
    Publication date: May 2, 2013
    Inventors: Avinash Srikrishnan Kashyap, David Mulford Shaddock, Emad Andarawis Andarawis, Peter Micah Sandvik, Stephen Daley Arthur, Vinayak Tilak
  • Patent number: 8425858
    Abstract: An apparatus includes an article and a detector. The article includes a substrate, a faceted structure disposed on the substrate, and a sensor layer disposed on the faceted structure. The faceted structure is disposed on the substrate first surface and itself has a surface. The faceted structure surface has peripheral edge defining a diameter of the faceted structure surface. The sensor layer is disposed on the faceted structure surface. The sensor layer can react or can interact with a target species when the target species is sufficiently proximate to the sensor layer. The sensor layer responds to the reaction or to the interaction in a detectable manner. The detector detects a response to the reaction, or to the interaction, of the target species with the sensor layer.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: April 23, 2013
    Assignee: Morpho Detection, Inc.
    Inventors: Steven Francis LeBoeuf, Peter Micah Sandvik, Radislav Alexandrovich Potyrailo
  • Patent number: 8357945
    Abstract: There is provided a GaN single crystal at least about 2.75 millimeters in diameter, with a dislocation density less than about 104 cm?1, and having substantially no tilt boundaries. A method of forming a GaN single crystal is also disclosed. The method includes providing a nucleation center, a GaN source material, and a GaN solvent in a chamber. The chamber is pressurized. First and second temperature distributions are generated in the chamber such that the solvent is supersaturated in the nucleation region of the chamber. The first and second temperature distributions have different temperature gradients within the chamber.
    Type: Grant
    Filed: October 26, 2006
    Date of Patent: January 22, 2013
    Assignee: Momentive Performance Materials Inc.
    Inventors: Mark Philip D'Evelyn, Dong-Sil Park, Steven Francis LeBoeuf, Larry Burton Rowland, Kristi Jean Narang, Huicong Hong, Peter Micah Sandvik
  • Publication number: 20120171824
    Abstract: A method of manufacturing a heterostructure device is provided that includes implantation of ions into a portion of a surface of a multi-layer structure. Iodine ions are implanted between a first region and a second region to form a third region. A charge is depleted from the two dimensional electron gas (2DEG) channel in the third region to form a reversibly electrically non-conductive pathway from the first region to the second region. On applying a voltage potential to a gate electrode proximate to the third region allows electrical current to flow from the first region to the second region.
    Type: Application
    Filed: March 13, 2012
    Publication date: July 5, 2012
    Inventors: Vinayak Tilak, Alexei Vertiatchikh, Kevin Sean Matocha, Peter Micah Sandvik, Siddharth Rajan
  • Patent number: 8198650
    Abstract: A semiconductor device is disclosed. The semiconductor device comprises, a first region of a first conductivity type, a second region of a second conductivity type disposed adjacent to the first region to form a p-n junction structure, a resistance modification region of the second conductivity type, and a field response modification region of the second conductivity type disposed between the resistance modification region and the second region, wherein the field response modification region comprises a varying dopant concentration distribution along a thickness direction of the field response modification region.
    Type: Grant
    Filed: December 8, 2008
    Date of Patent: June 12, 2012
    Assignee: General Electric Company
    Inventors: Stanislav Ivanovich Soloviev, Ho-Young Cha, Peter Micah Sandvik, Alexey Vert, Jody Alan Fronheiser
  • Patent number: 8159002
    Abstract: A heterostructure device includes a semiconductor multi-layer structure that has a first region, a second region and a third region. The first region is coupled to a source electrode and the second region is coupled to a drain electrode. The third region is disposed between the first region and the second region. The third region provides a switchable electrically conductive pathway from the source electrode to the drain electrode. The third region includes iodine ions. A system includes a heterostructure field effect transistor that includes the device.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: April 17, 2012
    Assignee: General Electric Company
    Inventors: Vinayak Tilak, Alexei Vertiatchikh, Kevin Sean Matocha, Peter Micah Sandvik, Siddharth Rajan
  • Publication number: 20110221456
    Abstract: A sensor system, and an associated method for detecting harsh environmental conditions, is provided. The sensor system includes at least one sensor having an electrical sensing element. The electrical sensing element is based on certain classes of composite materials: (a) silicon carbide (SiC); (Mo,W)5Si3C; (Mo,W)Si2; or (b) (Mo,W)5Si3C; (Mo,W)Si2; (Mo,W)5Si3. The sensor system is useful for determining harsh environmental conditions. Gasification systems, which include at least one of the sensor systems are also described.
    Type: Application
    Filed: March 11, 2010
    Publication date: September 15, 2011
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Jody Alan Fronheiser, Don Mark Lipkin, Peter Micah Sandvik, Todd Michael Striker, Martin Mathew Morra
  • Publication number: 20110138813
    Abstract: The present invention discloses a combustor system and method of measuring impurities in the combustion system. The combustion system includes an up-stream fuel injection point; a down-stream turbine combustor; a flame zone in the turbine combustor comprising a plurality of axial sub-zones; an optical port assembly configured to obtain a non-axial, direct, optical view of at least one of the plurality of axial sub-zones, and an impurity detection system in optical communication with the optical port assembly.
    Type: Application
    Filed: December 11, 2009
    Publication date: June 16, 2011
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Peter Micah Sandvik, Richard Dale Slates, Alexey Vasily Vert, Samer Aljabari
  • Patent number: 7906427
    Abstract: There is provided a method for dimension profiling of a semiconductor device. The method involves incorporating a feature comprising a detectable element into the device, and thereafter detecting the detectable element to determine a dimension of the feature. This information can be used for the determination of a dimension of buried channels, and also for end-point detection of CMP processes.
    Type: Grant
    Filed: October 14, 2008
    Date of Patent: March 15, 2011
    Assignee: General Electric Company
    Inventors: Jody Alan Fronheiser, Peter Micah Sandvik, Kevin Sean Matocha, Vinayak Tilak
  • Patent number: 7859008
    Abstract: A crystalline composition is provided that includes gallium and nitrogen. The crystalline composition may have an amount of oxygen present in a concentration of less than about 3×1018 per cubic centimeter, and may be free of two-dimensional planar boundary defects in a determined volume of the crystalline composition. The volume may have at least one dimension that is about 2.75 millimeters or greater, and the volume may have a one-dimensional linear defect dislocation density of less than about 10,000 per square centimeter.
    Type: Grant
    Filed: January 9, 2007
    Date of Patent: December 28, 2010
    Assignee: Momentive Performance Materials Inc.
    Inventors: Mark Philip D'Evelyn, Dong-Sil Park, Steven Francis LeBoeuf, Larry Burton Rowland, Kristi Jean Narang, Huicong Hong, Stephen Daley Arthur, Peter Micah Sandvik
  • Patent number: 7786503
    Abstract: A crystal comprising gallium nitride is disclosed. The crystal has at least one grain having at least one dimension greater than 2.75 mm, a dislocation density less than about 104 cm?2, and is substantially free of tilt boundaries.
    Type: Grant
    Filed: November 13, 2006
    Date of Patent: August 31, 2010
    Assignee: Momentive Performance Materials Inc.
    Inventors: Mark Philip D'Evelyn, Dong-Sil Park, Steven Francis LeBoeuf, Larry Burton Rowland, Kristi Jean Narang, Huicong Hong, Stephen Daley Arthur, Peter Micah Sandvik
  • Publication number: 20100140730
    Abstract: A semiconductor device is disclosed. The semiconductor device comprises, a first region of a first conductivity type, a second region of a second conductivity type disposed adjacent to the first region to form a p-n junction structure, a resistance modification region of the second conductivity type, and a field response modification region of the second conductivity type disposed between the resistance modification region and the second region, wherein the field response modification region comprises a varying dopant concentration distribution along a thickness direction of the field response modification region.
    Type: Application
    Filed: December 8, 2008
    Publication date: June 10, 2010
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Stanislav Ivanovich Soloviev, Ho-Young Cha, Peter Micah Sandvik, Alexey Vert, Jody Alan Fronheiser
  • Publication number: 20100093116
    Abstract: There is provided a method for dimension profiling of a semiconductor device. The method involves incorporating a feature comprising a detectable element into the device, and thereafter detecting the detectable element to determine a dimension of the feature. This information can be used for the determination of a dimension of buried channels, and also for end-point detection of CMP processes.
    Type: Application
    Filed: October 14, 2008
    Publication date: April 15, 2010
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Jody Alan Fronheiser, Peter Micah Sandvik, Kevin Sean Matocha, Vinayak Tilak
  • Patent number: 7638815
    Abstract: A crystalline composition is provided. The crystalline composition may include gallium and nitrogen; and the crystalline composition may have an infrared absorption peak at about 3175 cm?1, with an absorbance per unit thickness of greater than about 0.01 cm?1.
    Type: Grant
    Filed: January 9, 2007
    Date of Patent: December 29, 2009
    Assignee: Momentive Performance Materials Inc.
    Inventors: Mark Philip D'Evelyn, Dong-Sil Park, Steven Francis LeBoeuf, Larry Burton Rowland, Kristi Jean Narang, Huicong Hong, Stephen Daley Arthur, Peter Micah Sandvik
  • Publication number: 20090159929
    Abstract: A heterostructure device includes a semiconductor multi-layer structure that has a first region, a second region and a third region. The first region is coupled to a source electrode and the second region is coupled to a drain electrode. The third region is disposed between the first region and the second region. The third region provides a switchable electrically conductive pathway from the source electrode to the drain electrode. The third region includes iodine ions. A system includes a heterostructure field effect transistor that includes the device.
    Type: Application
    Filed: December 20, 2007
    Publication date: June 25, 2009
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Vinayak Tilak, Alexei Vertiatchikh, Kevin Sean Matocha, Peter Micah Sandvik, Siddharth Rajan
  • Patent number: 7547953
    Abstract: Gallium oxide films for sensing gas comprise Ga2O3 and have a porosity of at least about 30%. Such films can be formed by coating a substrate with a solution comprising: a gallium salt and a porogen comprising an organic compound comprising a hydrophilic chain and a hydrophobic chain; and heating the substrate to a temperature in the range from about 400° C. to about 600° C. while exposing the substrate to an oxygen-containing source to convert the gallium salt to a gallium oxide.
    Type: Grant
    Filed: January 29, 2007
    Date of Patent: June 16, 2009
    Assignee: General Electric Company
    Inventors: Anthony Yu-Chung Ku, Steven Alfred Tysoe, Vinayak Tilak, Peter Micah Sandvik, Sergio Paulo Martins Loureiro, James Anthony Ruud, Anis Zribi, Wei-Cheng Tian