Patents by Inventor Peter R. Holloway

Peter R. Holloway has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10995820
    Abstract: A flywheel apparatus that magnetically unloads a top rotor bearing is described. The apparatus includes a flywheel housing, a rotor with a vertical axis of rotation that includes a magnetic material, a magnet configured to apply a desired upward off-loading force along the vertical axis of rotation, an upper bearing connected to an upper shaft of the rotor, and a bearing housing disposed between the upper bearing and the flywheel housing that substantially prevents downward axial motion of the upper bearing. The magnet includes an electromagnet. A force sensor is used to measure a force on the upper bearing which is provided as input to a controller that updates the current to the electromagnet. The rotor is maintained in a fixed axial position and a spring disposed below a lower bearing absorbs axial dimension growth of the rotor.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: May 4, 2021
    Inventors: Seth R. Sanders, Peter Thomas Tennessen, Daniel Bakholdin, Matthew Brandon Garten, Mark J. Holloway, Matthew K. Senesky
  • Patent number: 7443226
    Abstract: A current source for generating a PTAT current using two bipolar transistors with an 1:A emitter area ratio implements a split resistor architecture to cancel mismatch errors in the current mirror of the current source. In one embodiment, a first resistor is coupled to the unit area bipolar transistor and a second resistor is coupled to the A-ratio-area bipolar transistor. The first resistor has a resistance value indicative of the emitter resistance re of the bipolar transistors while the second resistor has a resistance value satisfying the equation re*(lnA?1). In another embodiment, an emitter area trim scheme is applied in a PTAT current source to cancel, in one trim operation, both bipolar transistor area mismatch error and sheet resistance variations. The emitter area trim scheme operates to modify the emitter area of the A-ratio-area bipolar transistor to select the best effective emitter area that provides the most accurate PTAT current.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: October 28, 2008
    Assignee: National Semiconductor Corporation
    Inventors: Peter R. Holloway, Jun Wan
  • Patent number: 7385426
    Abstract: A buffer circuit (318) including a first half circuit and a second half circuit. Each half circuit includes a first MOS transistor (M4, M9) as the input device and a source follower, a second MOS transistor (M23, M22) as a transconductance amplifier device, and a third MOS transistor (M5, M8) as a folded cascode device. The first half circuit receives a buffer input voltage as the input voltage and the second half circuit receives a reference voltage as the input voltage. The first and second half circuits providing a pair of differential output signals indicative of the buffer input voltage. The buffer circuit has a very low input capacitance where the input capacitance does not vary with the buffer input voltage and other operating conditions, such as fabrication process, temperature and power supply voltage variations.
    Type: Grant
    Filed: February 26, 2007
    Date of Patent: June 10, 2008
    Assignee: National Semiconductor Corporation
    Inventors: Jun Wan, Peter R. Holloway
  • Patent number: 7372392
    Abstract: A method for charge balancing in a current input ADC including maintaining a low capacitance value at the integrator output node where the capacitance value is independent of the integrator output voltage and operating conditions, generating a first voltage pedestal at a first active device switch at the end of the autozero phase having a first voltage polarity and a first magnitude, generating a second voltage pedestal at a second active device switch at the end of the integration phase having an opposite voltage polarity and the first magnitude, and summing the first voltage pedestal with the second voltage pedestal. The difference between the first voltage pedestal and the second voltage pedestal results in a net voltage error. The first and second voltage pedestals have the first magnitude under all operating conditions of the modulator and the two voltage pedestals cancel to yield a small net voltage error.
    Type: Grant
    Filed: February 26, 2007
    Date of Patent: May 13, 2008
    Assignee: National Semiconductor Corporation
    Inventors: Jun Wan, Peter R. Holloway
  • Patent number: 7236048
    Abstract: A current source for generating a PTAT current using two bipolar transistors with an 1:A emitter area ratio implements a split resistor architecture to cancel mismatch errors in the current mirror of the current source. In one embodiment, a first resistor is coupled to the unit area bipolar transistor and a second resistor is coupled to the A-ratio-area bipolar transistor. The first resistor has a resistance value indicative of the emitter resistance re of the bipolar transistors while the second resistor has a resistance value satisfying the equation re*(lnA?1). In another embodiment, an emitter area trim scheme is applied in a PTAT current source to cancel, in one trim operation, both bipolar transistor area mismatch error and sheet resistance variations. The emitter area trim scheme operates to modify the emitter area of the A-ratio-area bipolar transistor to select the best effective emitter area that provides the most accurate PTAT current.
    Type: Grant
    Filed: November 22, 2005
    Date of Patent: June 26, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Peter R. Holloway, Jun Wan
  • Patent number: 7119612
    Abstract: A dual-channel instrumentation amplifier includes two channels of PMOS transistor differential pairs which are configured in a Y-connection and cross-coupled to two diode-connected NMOS transistors. Each input channel has a non-linear voltage-current characteristic. But when the differential currents cancel at the NMOS transistor diodes, both input channels have the same differential input voltage, regardless of any non-linearity. As thus configured, a high accuracy instrumentation amplifier which operates in current mode is realized with excellent DC matching and high common mode rejection ratio. In one embodiment, the dual-channel instrumentation amplifier is used as input stage for the linear comparator to enable the linear comparator to operate at a high rate of speed with excellent channel matching.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: October 10, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Peter R. Holloway, Jun Wan
  • Patent number: 7075360
    Abstract: A super-PTAT current source receives a PTAT reference voltage as input. The PTAT reference voltage is combined with the gate-to-source voltage difference of two unequal-area input transistors and the combined voltage is imposed on a high negative temperature coefficient resistor to produce an output current that is super-PTAT. A current source supplies a bias current to the super-PTAT current source whereby excess current provided by the current source is consumed by closed loop adjustments. The super-PTAT current source generates a super-PTAT current having a constant slope, excellent stability and very good linearity. In one embodiment, the super-PTAT output current is mixed with a sub-PTAT current in a preselected ratio to generate output currents having exactly the desired temperature coefficient.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: July 11, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Peter R. Holloway, Jun Wan
  • Patent number: 7075353
    Abstract: A clock generator circuit incorporates a sub-PTAT (proportional to absolute temperature) current source and a super-PTAT current source for generating bias currents for a voltage reference generator and charging currents for a voltage ramp generator. The clock generator circuit further includes a linear comparator coupled to receive one or more switching voltage reference signals and a voltage ramp signal and generate a switching output signal as the clock signal. The clock signal is coupled to a clock decoder to generate the desired clock signals having the desired phase. The functional blocks of the clock generator circuit of the present invention operate together to generate a highly frequency stable clock signal. In one embodiment, the linear comparator incorporates a dual-differential-input (dual-channel) instrumentation amplifier as the comparator input stage to generate clock signals having clock frequency errors that are minimized over process, temperature and power supply variations.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: July 11, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Jun Wan, Peter R. Holloway
  • Patent number: 7015744
    Abstract: A self-regulating current source is formed by a PMOS current mirror and an interconnected pair of NMOS transistors. The NMOS transistors are sized differently and forced to operate at similar currents. The difference of the Vgs voltages of the NMOS transistors is impressed across the resistor to develop a stable output current. In particular, the current source starts reliably at low supply voltages and operates to reliably generate a stable low output current at a well-controlled operating point. The self-regulating current source can be used effectively as the watchdog current source of a power-on reset circuit to ensure reliable and robust operation even at low Vdd voltage values.
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: March 21, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Peter R. Holloway, Jun Wan
  • Patent number: 7015732
    Abstract: A power-on reset circuit for an integrated circuit includes a voltage threshold detector circuit for generating a first signal, a DC biasing start-up circuit providing start-up currents and a first control signal, a self-regulating watchdog current source providing bias currents and a counter circuit for counting a predetermined number of cycles when enabled by the first control signal and providing a second control signal when the count is completed. The POR circuit asserts the reset signal when the first signal is asserted and deasserts the reset signal when both the first signal and the second control signal are deasserted. The POR circuit merges accurate detection of the full range of Vdd events with a self-adapting current source. In addition, the POR circuit employs “pulse-stretching” techniques operating independently but mutually working together to create a POR assertion persistence in the time domain that further enhances the reliability of POR signal effectiveness.
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: March 21, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Peter R. Holloway, Jun Wan
  • Patent number: 6962436
    Abstract: A digitizing temperature measurement system for providing a digital temperature measurement includes an excitation source for providing switched excitation currents to two or three temperature sensing elements and an ADC circuit including a charge-balancing modulator and a digital post processing circuit. The system utilizes synchronous AC excitation of the temperature sensing elements and an AC coupled analog-to-digital converter input. The temperature measurement system also implements correlated double sampling for noise cancellation to provide low noise and highly accurate analog-to-digital conversions. The modulator receives a charge domain reference signal generated by a reference charge packet generator incorporating a charge based bandgap subsystem. Therefore, the temperature measurement system can be operated at very low supply voltages, such as 1.0 Vdc.
    Type: Grant
    Filed: March 17, 2005
    Date of Patent: November 8, 2005
    Assignee: National Semiconductor Corporation
    Inventors: Peter R. Holloway, Eric D. Blom, Jun Wan, Stuart H. Urie
  • Patent number: 6957910
    Abstract: A circuit in an integrated circuit for measuring temperature dependent voltages of a temperature sensing element includes a voltage generator circuit providing the temperature dependent voltages, a first sampling switch and a second sampling switch. The voltage generator circuit includes a temperature sensing element being excited by a first switched current and a second switched current. The first and second sampling switches sample a first voltage and a second voltage at the temperature sensing element while the temperature sensing element is being excited by the second current and the first current, respectively. Each of the first and second sampling switches includes a boosted switch circuit incorporating a pedestal voltage compensation circuit. The sampled first and second voltages are coupled to be stored on capacitors external to the integrated circuit. The difference between the first voltage and the second voltage is measured to determine the temperature of the integrated circuit.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: October 25, 2005
    Assignee: National Semiconductor Corporation
    Inventors: Jun Wan, Peter R. Holloway, Gary E. Sheehan
  • Patent number: 6956411
    Abstract: A low distortion, high frequency switch circuit for selectively coupling an input voltage terminal to an output voltage terminal includes a switching device coupled to the input voltage terminal and the output voltage terminal, a charge storage device, and a first, second and third switches. While the switch circuit is turned off, the charge storage device, typically a capacitor, is charged to a precharge voltage. Then, when the switch circuit is to be turned on, the charge storage device is coupled between the control terminal of the switching device and the input voltage terminal. As a result, the switching device receives a constant gate-to-source voltage approximately equals to the precharge voltage and becomes conductive with a minimum and constant RON for all values of input voltages. In another embodiment, the switch circuit includes a pedestal voltage compensation circuit for reducing charge injection induced pedestal errors.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: October 18, 2005
    Assignee: National Semiconductor Corporation
    Inventor: Peter R. Holloway
  • Patent number: 6930495
    Abstract: A digitizing ohmmeter system for providing a digital resistance measurement includes a current source for providing an excitation current to an impedance-varying input sensor and an ADC circuit including a charge-balancing modulator and a digital post processing circuit. The system utilizes synchronous AC excitation of the input sensor and an AC coupled analog-to-digital converter input. The digitizing ohmmeter system also implements correlated double sampling for noise cancellation to provide low noise and highly accurate analog-to-digital conversions. The ADC circuit includes a reference signal generator generating a resistance reference signal by time-sharing the excitation current with the input sensor. The digitizing ohmmeter system thereby realizes fully ratiometric operation such that neither a precise current source nor a precise voltage source is required for accurate resistance measurements.
    Type: Grant
    Filed: June 16, 2004
    Date of Patent: August 16, 2005
    Assignee: National Semiconductor Corporation
    Inventors: Eric D. Blom, Peter R. Holloway, Jun Wan, Stuart H. Urie
  • Patent number: 6903558
    Abstract: A digitizing ohmmeter system for providing a digital resistance measurement includes a current source for providing an excitation current to an impedance-varying input sensor and an ADC circuit including a charge-balancing modulator and a digital post processing circuit. The system utilizes synchronous AC excitation of the input sensor and an AC coupled analog-to-digital converter input. The digitizing ohmmeter system also implements correlated double sampling for noise cancellation to provide low noise and highly accurate analog-to-digital conversions. The ADC circuit includes a reference signal generator generating a resistance reference signal by time-sharing the excitation current with the input sensor. The digitizing ohmmeter system thereby realizes fully ratiometric operation such that neither a precise current source nor a precise voltage source is required for accurate resistance measurements.
    Type: Grant
    Filed: April 25, 2003
    Date of Patent: June 7, 2005
    Assignee: National Semiconductor Corporation
    Inventors: Eric D. Blom, Peter R. Holloway, Jun Wan, Stuart H. Urie
  • Patent number: 6869216
    Abstract: A digitizing temperature measurement system for providing a digital temperature measurement includes an excitation source for providing switched excitation currents to two or three temperature sensing elements and an ADC circuit including a charge-balancing modulator and a digital post processing circuit. The system utilizes synchronous AC excitation of the temperature sensing elements and an AC coupled analog-to-digital converter input. The temperature measurement system also implements correlated double sampling for noise cancellation to provide low noise and highly accurate analog-to-digital conversions. The modulator receives a charge domain reference signal generated by a reference charge packet generator incorporating a charge based bandgap subsystem. Therefore, the temperature measurement system can be operated at very low supply voltages, such as 1.0 Vdc.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: March 22, 2005
    Assignee: National Semiconductor Corporation
    Inventors: Peter R. Holloway, Eric D. Blom, Jun Wan, Stuart H. Urie
  • Patent number: 6831504
    Abstract: A current source includes a first circuit branch of a pair of diode-connected transistors with a resistor connected at the drain terminal and a second circuit branch of an inverter pair of transistors. Both of the circuit branches are supplied by a first current source powered by a supply voltage. The transistors are biased in the subthreshold region and have non-nominal size ratios. A first voltage and a second voltage are established across the resistor and the voltage difference causes a current proportional to absolute temperature to flow in the resistor. The second circuit branch functions as an error amplifier providing an “error signal” to facilitate voltage regulation. The regulation is realized in a third circuit branch which receives the “error signal” and draws excess current from the first current source so that the first voltage and the second voltage remain at the ideal regulated operation point.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: December 14, 2004
    Assignee: National Semiconductor Corporation
    Inventors: Peter R. Holloway, Eric D. Blom, Jun Wan
  • Patent number: 6831925
    Abstract: A structure and process are provided for using a single wire or data bus to detect collisions between two communication nodes connected by the single wire by sensing current changes in the wire, where large current changes indicate a collision. When a second node wants to obtain control of the wire on which a first node is transmitting data, the second node transmits a special data packet to ensure a collision and cause a large current to flow on the wire. Once a large current is detected in the wire to indicate a bit difference or collision, the first node stops transmitting and waits until it receives a synchronization bit pattern, which will indicate that the special data packet transmitted by the second node has ended. The two nodes are now synchronized, such that the second node has control of the wire and can begin transmission of a data packet. In order to indicate a collision, the large current flow must remain high after a specified time interval, such as a clock cycle.
    Type: Grant
    Filed: April 6, 1999
    Date of Patent: December 14, 2004
    Assignee: National Semiconductor Corporation
    Inventors: Ravi Subrahmanyan, Mark L. Seiders, Peter R. Holloway
  • Patent number: 6750796
    Abstract: A charge balancing modulation system for digitizing the output of a variable impedance sensor utilizes synchronous excitation of the input sensor and AC coupling of the analog input signal. The modulation system also implements correlated double sampling to provide low noise and highly accurate analog-to-digital conversions. In one embodiment, the modulation system includes an excitation source for providing a switched current to the input sensor and generating an input voltage step in response, and an integrator including an input capacitor, an amplifier and an accumulation capacitor. The input capacitor AC couples the analog input signal to the integrator. The integrator is controlled by switches operating in complementary state for enabling correlated double sampling operation or enabling data dependent charge accumulation operation. The modulation system generates an output data stream exhibiting a ones density proportional to the magnitude of the average input voltage step.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: June 15, 2004
    Assignee: National Semiconductor Corporation
    Inventors: Peter R. Holloway, Eric D. Blom, Jun Wan
  • Patent number: 6373330
    Abstract: A bandgap voltage reference circuit with no error amplifier circuit includes a chain of complementary emitter follower circuits that are connected to a supply voltage and to common ground via respective current mirrors. Each emitter follower circuit within the chain of emitter follower circuits generates a base to emitter voltage. Because of the successive configuration of the chain of emitter follower circuits, the base to emitter voltage differences from all the emitter follower circuits are summed together. Using a chosen number of emitter follower circuits along with an appropriately chosen area for the emitters of the transistors within the emitter follower circuits, the desired proportional to absolute temperature voltage is generated. Further, because of the additive nature of the base to emitter voltage differences, as opposed to a multiplicative nature as found in conventional circuits, the bandgap voltage reference circuit has a decreased level of noise and process sensitivity.
    Type: Grant
    Filed: January 29, 2001
    Date of Patent: April 16, 2002
    Assignee: National Semiconductor Corporation
    Inventor: Peter R. Holloway