Abstract: Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.

Abstract: Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND component is obtained in response to receiving the command. The command is then executed to write data to the NAND component and to write a representation of the temperature. The data is written to a user portion and the representation of the temperature is written to a management portion that is accessible only to the controller and segregated from the user portion.

Abstract: A processing device in a memory system incrementally adjusts a center read voltage for a first block of a memory device by a first offset amount to generate an adjusted read voltage and causes the adjusted read voltage to be applied to the first block to determine an adjusted bit count associated with the adjusted read voltage. The processing device further determines whether a difference between the adjusted bit count and a previous bit count associated with a previous read voltage satisfies a first threshold criterion pertaining to an error threshold, and responsive to the difference between the adjusted bit count and the previous bit count not satisfying the first threshold criterion, determines a read window for the first block based on the previous read voltage.

Abstract: A processing device in a memory system determines a rate at which an amount of valid data is decreasing on a first block of the memory device and determines whether the rate at which the amount of valid data is decreasing on the first block satisfies a threshold criterion. Responsive to the rate at which the amount of valid data is decreasing on the first block satisfying the threshold criterion, the processing device performs a media management operation on the first block of the memory device.

Abstract: A processing device in a memory system receives a memory command indicating a read window size and a first read voltage and identifies a read window for a first data block of the memory component having the read window size and centered at the first read voltage. The processing device determines whether a number of bit flips for the first data block within the read window exceeds an error threshold and, in response to the number of bit flips exceeding the error threshold, refreshes data stored on the first data block of the memory component.

Abstract: Some embodiments include apparatuses and methods for activating a signal associated with an access line coupled to different groups of memory cells during a memory operation of a device, and for sensing data lines of the device during different time intervals of the memory operation to determine the value of information stored in the memory cells. Each of the data lines can be coupled to a respective memory cell of each of the groups of memory cells. In at least one of such apparatuses and methods, the signal applied to the access line can remain activated during the memory operation.

Abstract: A processing device in a memory system determines whether a first data block of a plurality of data blocks on the memory component satisfies a first threshold criterion pertaining to a first number of the plurality of data blocks having a lower amount of valid data than a remainder of the plurality of data blocks. Responsive to the first data block satisfying the first threshold criterion, the processing device determines whether the first data block satisfies a second threshold criterion pertaining to a second number of the plurality of data blocks having been written to more recently than the remainder of the plurality of data blocks. Responsive to the first data block satisfying the second threshold criterion, the processing device determines whether a rate of change of an amount of valid data on the first data block satisfies a third threshold criterion.

Abstract: Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.

Abstract: Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.

Abstract: Systems and methods are disclosed, comprising a memory device comprising multiple groups of memory cells, the groups comprising a first group of memory cells and a second group of memory cells configured to store information at a same bit capacity per memory cell, and a processing device operably coupled to the memory device, the processing device configured to adjust a scan event threshold for one of the first or second groups of memory cells to a threshold less than a target scan event threshold for the first and second groups of memory cells to distribute scan events in time on the memory device.

Abstract: Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND component is obtained in response to receiving the command. The command is then executed to write data to the NAND component and to write a representation of the temperature. The data is written to a user portion and the representation of the temperature is written to a management portion that is accessible only to the controller and segregated from the user portion.

Abstract: A processing device in a memory system receives a memory command indicating a read window size and a first read voltage and identifies a read window for a first data block of the memory component having the read window size and centered at the first read voltage. The processing device determines whether a number of bit flips for the first data block within the read window exceeds an error threshold and, in response to the number of bit flips exceeding the error threshold, refreshes data stored on the first data block of the memory component.

Abstract: A processing device in a memory system determines whether a first data block of a plurality of data blocks on the memory component satisfies a first threshold criterion pertaining to a first number of the plurality of data blocks having a lower amount of valid data than a remainder of the plurality of data blocks. Responsive to the first data block satisfying the first threshold criterion, the processing device determines whether the first data block satisfies a second threshold criterion pertaining to a second number of the plurality of data blocks having been written to more recently than the remainder of the plurality of data blocks. Responsive to the first data block satisfying the second threshold criterion, the processing device determines whether a rate of change of an amount of valid data on the first data block satisfies a third threshold criterion.

Abstract: Systems and methods are disclosed, comprising a memory device comprising multiple groups of memory cells, the groups comprising a first group of memory cells and a second group of memory cells configured to store information at a same bit capacity per memory cell, and a processing device operably coupled to the memory device, the processing device configured to adjust a scan event threshold for one of the first or second groups of memory cells to a threshold less than a target scan event threshold for the first and second groups of memory cells to distribute scan events in time on the memory device.

Abstract: Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND component is obtained in response to receiving the command. The command is then executed to write data to the NAND component and to write a representation of the temperature. The data is written to a user portion and the representation of the temperature is written to a management portion that is accessible only to the controller and segregated from the user portion.

Abstract: Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.

Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus that include a memory device having read levels that can be calibrated. A calibration controller implemented with the memory device can trigger a read level calibration based on inputs from one or more trackers monitoring parameters associated with the memory device and a determination of an occurrence of at least one event from a set of events related to the monitored parameters. The monitored parameters can include parameters related to a selected time interval and measurements of read, erase, or write operations of the memory device. Additional apparatus, systems, and methods are disclosed.

Abstract: Methods and apparatuses are disclosed, such as those including a block of memory cells that includes strings of charge storage devices. Each of the strings may comprise a plurality of charge storage devices formed in a plurality of tiers. The apparatus may comprise a plurality of access lines shared by the strings. Each of the plurality of access lines may be coupled to the charge storage devices corresponding to a respective tier of the plurality of tiers. The apparatus may comprise a plurality of sub-sources associated with the strings. Each of the plurality of sub-sources may be coupled to a source select gate of each string of a respective subset of a plurality of subsets of the strings, and each sub-source may be independently selectable from other sub-sources to select the strings of its respective subset independently of other strings corresponding to other subsets.

Abstract: An amount of valid data for each data block of multiple data blocks stored at a first memory is determined. An operation to write valid data of a particular data block from the first memory to a second memory is performed based on the amount of valid data for each data block. A determination is made that a threshold condition associated with when valid data of the data blocks was written to the first memory has been satisfied. In response to determining that the threshold condition has been satisfied, the operation to write valid data of the data blocks from the first memory to the second memory is performed based on when the valid data was written to the first memory.

Abstract: Systems and methods are disclosed, comprising a memory device comprising multiple groups of memory cells, the groups comprising a first group of memory cells and a second group of memory cells configured to store information at a same bit capacity per memory cell, and a processing device operably coupled to the memory device, the processing device configured to adjust a scan event threshold for one of the first or second groups of memory cells to a threshold less than a target scan event threshold for the first and second groups of memory cells to distribute scan events in time on the memory device.