Patents by Inventor Peter Vlasenko
Peter Vlasenko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080130177Abstract: A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors. Each of first and second pairs of transistors in the circuit can provide an additional path for current from its associated one of the switching circuitry transistors during off-switching of that transistor so that a spike in current from the switching circuitry transistor is only partially transmitted through a path extending between the switching circuitry transistor and a capacitor of the charge pump.Type: ApplicationFiled: November 30, 2006Publication date: June 5, 2008Applicant: MOSAID TECHNOLOGIES, INCORPORATEDInventors: Peter Vlasenko, Huy Tuong Mai
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Publication number: 20080089459Abstract: A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.Type: ApplicationFiled: December 4, 2007Publication date: April 17, 2008Applicant: MOSAID Technologies, Inc.Inventors: Peter Vlasenko, Dieter Haerle
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Patent number: 7336752Abstract: A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.Type: GrantFiled: December 31, 2002Date of Patent: February 26, 2008Assignee: MOSAID Technologies Inc.Inventors: Peter Vlasenko, Dieter Haerle
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Publication number: 20080030247Abstract: A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.Type: ApplicationFiled: October 4, 2007Publication date: February 7, 2008Inventors: Dieter Haerle, Tony Mai, Peter Vlasenko
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Patent number: 7285997Abstract: A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.Type: GrantFiled: January 29, 2007Date of Patent: October 23, 2007Assignee: Mosaid Technologies, Inc.Inventors: Dieter Haerle, Tony Mai, Peter Vlasenko
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Publication number: 20070120587Abstract: A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.Type: ApplicationFiled: January 29, 2007Publication date: May 31, 2007Inventors: Dieter Haerle, Tony Mai, Peter Vlasenko
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Publication number: 20070079147Abstract: A power up circuit that having reduced power consumption during power saving modes, while maintaining an active flag signal indicating that the power supply voltage is satisfactory. This is achieved by turning off the power up circuit during the power saving mode, and using a status holding circuit to maintain the active flag signal in response to the power down signal. The status holding circuit is responsive to an internal node of the power up circuit for generating the active flag signal when the internal node has reached a predetermined level. The power down signal can be one or both a sleep mode signal and a deep power down signal. The status holding comprises an override circuit for maintaining the active flag signal in the power saving mode, and a restore circuit for rapidly resetting at least the internal node of the power up circuit upon exit of the power saving mode.Type: ApplicationFiled: September 30, 2005Publication date: April 5, 2007Inventors: Hong-Beom Pyeon, Peter Vlasenko
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Patent number: 7190201Abstract: A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.Type: GrantFiled: February 3, 2005Date of Patent: March 13, 2007Assignee: Mosaid Technologies, Inc.Inventors: Dieter Haerle, Tony Mai, Peter Vlasenko
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Publication number: 20060170471Abstract: A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.Type: ApplicationFiled: February 3, 2005Publication date: August 3, 2006Applicant: MOSAID Technologies, Inc.Inventors: Dieter Haerle, Tony Mai, Peter Vlasenko
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Publication number: 20040125905Abstract: A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.Type: ApplicationFiled: December 31, 2002Publication date: July 1, 2004Applicant: MOSAID Technologies, Inc.Inventors: Peter Vlasenko, Dieter Haerle
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Patent number: 6717876Abstract: A matchline sense circuit for detecting a current on a matchline of a CAM array is disclosed. Matchlines are decoupled from the sense circuit sense node in order to achieve higher sensing speed and improved sense margins. More specifically, a matchline sense circuit sense node receives a reference current, which is high enough to maintain the sense node at the high logic level. This reference current is generated from a dummy pull-down path identical to a memory cell pull-down path to ensure that the reference current tracks with changes to the memory cell current. Matchlines initially at ground potential undergo accelerated precharge up to a preset voltage potential level below VDD to overcome tail-out parasitic current and to minimize the voltage swing of the matchlines for conserving power. During sensing, the matchline current is compared to the reference current, and a latch circuit connected to the sense node provides a full CMOS output signal indicating the result of the comparison.Type: GrantFiled: December 27, 2002Date of Patent: April 6, 2004Assignee: Mosaid Technologies IncorporatedInventors: Peter Vlasenko, Douglas Perry
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Patent number: 6665220Abstract: A system for adding redundancy to the data path of a content addressable memory array is disclosed herein. The disclosed system employs an array of memory elements, supplemented by an array of redundant memory elements, with a switching system and a redundancy control system to ensure that defective memory elements are not accessed. Additionally a pull down unit is employed on the search lines of non-operative memory elements to ensure that inaccurate search results are not reported.Type: GrantFiled: June 18, 2002Date of Patent: December 16, 2003Assignee: Mosaid Technologies IncorporatedInventor: Peter Vlasenko
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Publication number: 20030137890Abstract: A matchline sense circuit for detecting a current on a matchline of a CAM array is disclosed. Matchlines are decoupled from the sense circuit sense node in order to achieve higher sensing speed and improved sense margins. More specifically, a matchline sense circuit sense node receives a reference current, which is high enough to maintain the sense node at the high logic level. This reference current is generated from a dummy pull-down path identical to a memory cell pull-down path to ensure that the reference current tracks with changes to the memory cell current. Matchlines initially at ground potential undergo accelerated precharge up to a preset voltage potential level below VDD to overcome tail-out parasitic current and to minimize the voltage swing of the matchlines for conserving power. During sensing, the matchline current is compared to the reference current, and a latch circuit connected to the sense node provides a full CMOS output signal indicating the result of the comparison.Type: ApplicationFiled: December 27, 2002Publication date: July 24, 2003Inventors: Peter Vlasenko, Douglas Perry
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Patent number: 6584003Abstract: A low power CAM architecture is disclosed. Matchlines of the CAM array are sequential into a main search portion and a main search portion. After issuing a search command, a main search operation is conducted on the main search portion of the matchline. If the result of the main search is a match, then the main search is subsequently conducted on the main search portion of the matchline. If the result of main search is a mismatch, then the main search is disabled, and consequently there is no power dissipation on the main search portion of the matchlines. Main search and main search operations can be pipelined to maintain high throughput with minimum latency. Power consumption is further reduced by using a matchline sense circuit for detecting a current on the main search and main search portions of the matchline.Type: GrantFiled: April 30, 2002Date of Patent: June 24, 2003Assignee: Mosaid Technologies IncorporatedInventors: Jin-Ki Kim, Peter Vlasenko, Douglas Perry, Peter B. Gillingham
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Publication number: 20030081464Abstract: A system for adding redundancy to the data path of a content addressable memory array is disclosed herein. The disclosed system employs an array of memory elements, supplemented by an array of redundant memory elements, with a switching system and a redundancy control system to ensure that defective memory elements are not accessed. Additionally a pull down unit is employed on the search lines of non-operative memory elements to ensure that inaccurate search results are not reported.Type: ApplicationFiled: June 18, 2002Publication date: May 1, 2003Inventor: Peter Vlasenko
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Patent number: 6144591Abstract: This invention provides a data bit redundancy method and apparatus that permits the replacement of faulty bitlines on a data bit basis as opposed to a column address basis. This invention provides a semiconductor memory device having memory cells arranged in columns and rows. Normal local data lines are connected to a global data line via a first switch. A redundant memory data line is connected to the global data line via a second switch. A control generating first and second control signals are coupled to the respective first and second switches for operating the switch in response to a status of a fuse component, whereby when the fuse is intact the normal data lines are connected to the global data line and when the rise is blown the redundant data lines are connected to the global data line, thus not requiring additional redundancy address decoding circuitry.Type: GrantFiled: November 17, 1998Date of Patent: November 7, 2000Assignee: Mosaid Technologies IncorporatedInventors: Peter Vlasenko, John Wu, Arun Achyuthan, Guillaume Valcourt