Abstract: A solid-state protector circuit utilizes the combination of two zener diodes (Z1, Z2), a resistor (R1), a capacitor (C1), and a gated diode switch (GDS) to facilitate the rapid discharge of high voltage transients.

Abstract: To switch a first gated diode switch (GDS) to the "OFF" state requires a voltage applied to the gate which is more positive than that of the anode or cathode and the sourcing of current into the gate which is of the same order of magnitude as flows between the anode and cathode. Control circuitry, which uses a second GDS coupled by the cathode to the gate of the first GDS, is used to control the state of the first GDS. The state of the second GDS is controlled by a branch circuit having a relatively modest current handling capability. An n-p-n junction transistor has the emitter and collector coupled to the cathode and gate, respectively, of the first GDS, and has the base coupled through a p-n-p transistor to the input terminal of the control circuitry. The n-p-n transistor facilitates a quick turn-on of the first GDS by rapidly bringing the potentials of the gate and cathode of the first GDS to levels which are close together.

Abstract: A structure for achieving closely spaced high voltage devices in integrated circuits. The devices are formed in single crystalline tubs (11) in a polycrystalline substrate (10). In order to prevent the potential of the substrate from causing breakdown of the devices, there is included between the single crystalline tubs and the polycrystalline substrate a semi-insulating layer (13) which has trapping states capable of taking on charge from the single crystalline region. The shielding provided by the semi-insulating layer permits the surface regions of the device to be made closer to the polycrystalline substrate and the tubs to be made more shallow.

Abstract: Integrated circuit complementary transistors for high voltage switching applications are fabricated in separate dielectrically-isolated pockets (12), (14) of high resistivity silicon, supported in a conductive medium (11) such as polycrystalline silicon, using surface adjacent conductivity type zones constituting emitter (19), (23), base (16), (20) and collector zones (17), (21). In one embodiment using high resistivity (75-300 ohm cm) silicon, referred to as .pi. material, for the material of the pocket, one transistor is a PN.pi.P device, and the other is an NP.pi.N. In the PN.pi.P the reverse-biased base-collector pn junction is the interface between the N base zone (16) and the .pi. portion (12) of the collector zone. In the NP.pi.N transistor the base-collector junction is the interface between the lightly doped .pi. extension (14) of the base zone (20) and the N collector zone (21). A connection (32) is provided to the conductive substrate to enable application of a suitable potential thereto.

Abstract: Disclosed is a monolithic transistor circuit for high voltage applications. A high impedance bleed resistor is effectively provided across the emitter-base junction of one of the transistors. This is accomplished by placing the base regions of this and another transistor at a selected distance apart so that the zero bias depletion regions of the bases overlap to produce a punch through condition resulting in a desired current density therebetween when an external bias is supplied. The devices thus produced have a high current carrying capacity with low leakage currents.

Abstract: Disclosed are dielectrically isolated high voltage planar devices and methods of fabricating such devices. The devices are designed so that the large electric fields at the junction edges are significantly reduced; thereby permitting a closely packed structure. This concept may be achieved by forming narrow grooves at the junctions and filling with a thermally grown oxide. In a preferred embodiment, the surface of the devices lies in the (110) plane so that the walls of the grooves are perpendicular thereto in the (111) plane. Fabrication includes bonding the semiconductor wafer to a substrate with an oxide layer therebetween and forming grooves through the wafer to the oxide layer for isolation from device to device.

Abstract: A semiconductor junction-isolated PNPN crosspoint switch array has a plurality of crosspoint switches that are each formed of four regions of alternating conductivity type in a semiconductor substrate. Low enough leakage to allow the crosspoint switch array to be used in large telephone switching systems is achieved by proper selection of the thickness of the semiconductor regions and by appropriate gold doping thereof.