Patents by Inventor Petra Leber

Petra Leber has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11023205
    Abstract: Negative zero control for execution of an instruction. A process obtains an instruction to perform operation(s) using an input value. The instruction includes a negative zero control indicator indicating whether negative zero control is enabled for execution of the instruction. The process executes the instruction, the executing including performing the operation(s) using the input value to obtain a result having a sign, determining whether to control the sign of the result, the determining being based at least in part on the negative zero control indicator being set to a defined value, and performing further processing, as part the executing the instruction, based on the determining.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: June 1, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cedric Lichtenau, Reid Copeland, Petra Leber, Silvia M. Mueller, Jonathan D. Bradbury, Xin Guo
  • Patent number: 10996951
    Abstract: A method for detecting faults in substring search operations using a processor unit including vector registers of M vector elements each. A non-limiting example of the method includes providing an M×M matrix of comparators for characterwise comparison of the elements of a reference string and a target string. A first zero detect vector having value indicative of terminating element of the target string and a second zero detect vector having a value indicative of terminating element of the reference string are generated. A resulting bit vector is generated using comparison performed by the M×M matrix. The resulting bit vector indicates characters of the target string that fully match the reference string and indicate characters of the target string that partially match the reference string. Fault detection in the substring search operations is performed by comparing the generated zero detect vectors with operands.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: May 4, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Razvan Peter Figuli, Stefan Payer, Petra Leber, Cedric Lichtenau
  • Publication number: 20210072989
    Abstract: A method for detecting faults in substring search operations using a processor unit including vector registers of M vector elements each. A non-limiting example of the method includes providing an M×M matrix of comparators for characterwise comparison of the elements of a reference string and a target string. A first zero detect vector having value indicative of terminating element of the target string and a second zero detect vector having a value indicative of terminating element of the reference string are generated. A resulting bit vector is generated using comparison performed by the M×M matrix. The resulting bit vector indicates characters of the target string that fully match the reference string and indicate characters of the target string that partially match the reference string. Fault detection in the substring search operations is performed by comparing the generated zero detect vectors with operands.
    Type: Application
    Filed: September 11, 2019
    Publication date: March 11, 2021
    Inventors: RAZVAN PETER FIGULI, STEFAN PAYER, PETRA LEBER, CEDRIC LICHTENAU
  • Patent number: 10929213
    Abstract: In an approach for protecting recoding logic in a computing environment, a processor obtains an operand of an instruction in a first data format. A processor converts the operand from the first data format to a second data format. A processor generates a predicted residue of the operand in the second data format, wherein generating the predicted residue of the operand in the second data format comprises: generating a residue of the operand from the first data format.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: February 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Steven R. Carlough, Petra Leber, Daniel Lipetz, Silvia M. Mueller
  • Publication number: 20210042119
    Abstract: An aspect includes generating a data result and a special case indicator based on an instruction and at least one input data operand. Outputting the data result to a processor core. Outputting the first condition code to the processor core prior to outputting the data result to the processor core. Generating a second condition code based on the data result and the special case indicator. Performing a check by comparing the first condition code and the second condition code and flagging an error to the processor core upon the first condition code being different from the second condition code.
    Type: Application
    Filed: August 9, 2019
    Publication date: February 11, 2021
    Inventors: Petra Leber, Kerstin Claudia Schelm, Cedric Lichtenau, Michael Klein
  • Publication number: 20210042088
    Abstract: An aspect includes executing, by a binary based floating-point arithmetic unit of a processor, a calculation having two or more operands in hexadecimal format based on a hexadecimal floating-point (HFP) instruction and providing a condition code for a calculation result of the calculation. The floating-point arithmetic unit includes a condition code anticipator circuit that is configured to provide the condition code to the processor prior to availability of the calculation result.
    Type: Application
    Filed: August 9, 2019
    Publication date: February 11, 2021
    Inventors: Silvia Melitta Mueller, Petra Leber, Kerstin Claudia Schelm, Cedric Lichtenau
  • Patent number: 10915385
    Abstract: In an approach for protecting recoding logic in a computing environment, a processor obtains an operand of an instruction in a first data format. A processor converts the operand from the first data format to a second data format. A processor generates a predicted residue of the operand in the second data format, wherein generating the predicted residue of the operand in the second data format comprises: generating a residue of the operand from the first data format.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: February 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Steven R. Carlough, Petra Leber, Daniel Lipetz, Silvia M. Mueller
  • Publication number: 20210034325
    Abstract: A method includes dividing a fraction of a floating point result into a first portion and a second portion. The method includes outputting a first normalizer result based on the first portion during to a first clock cycle. The method includes storing a first segment of the first portion during to the first clock cycle. The method includes outputting a first rounder result based on the first normalizer result during to the first clock cycle. The method includes outputting a second normalizer result based on the second portion during to a second clock cycle. The method includes outputting a second rounder result based on the second normalizer result and the first segment during to the second clock cycle.
    Type: Application
    Filed: July 31, 2019
    Publication date: February 4, 2021
    Inventors: Nicol Hofmann, Michael Klein, Petra Leber, Kerstin Claudia Schelm
  • Publication number: 20200348908
    Abstract: Examples of techniques for hexadecimal exponent alignment for a binary floating point unit (BFU) of a computer processor are described herein. An aspect includes receiving, by the BFU, a first operand comprising a first fraction and a first exponent, and a second operand comprising a second fraction and a second exponent. Another aspect includes, based on the first operand and the second operand being in a first floating point format, multiplying each of the first exponent and the second exponent by a factor corresponding to a number of bits in a digit in the first floating point format.
    Type: Application
    Filed: April 30, 2019
    Publication date: November 5, 2020
    Inventors: Kerstin Claudia Schelm, Petra Leber, Nicol Hofmann, Michael Klein
  • Publication number: 20200264840
    Abstract: Negative zero control for execution of an instruction. A process obtains an instruction to perform operation(s) using an input value. The instruction includes a negative zero control indicator indicating whether negative zero control is enabled for execution of the instruction. The process executes the instruction, the executing including performing the operation(s) using the input value to obtain a result having a sign, determining whether to control the sign of the result, the determining being based at least in part on the negative zero control indicator being set to a defined value, and performing further processing, as part the executing the instruction, based on the determining.
    Type: Application
    Filed: February 15, 2019
    Publication date: August 20, 2020
    Inventors: Cedric LICHTENAU, Reid COPELAND, Petra LEBER, Silvia M. MUELLER, Jonathan D. BRADBURY, Xin GUO
  • Publication number: 20200264890
    Abstract: Digit validation check control for execution of an instruction. A process obtains an instruction to perform operation(s) using input value(s). The instruction includes a no validation indicator for controlling whether digit validation check control is enabled for execution of the instruction. The process executes the instruction, including determining, based on the no validation indicator, whether digit validation check control is enabled for execution of the instruction, and performing processing based on the determining. Based on the no validation indicator being set to a defined value, digit validation check control is enabled and the processing includes forcing a digit check error indicator output by the executing to indicate no digit check error with respect to the at least one input value.
    Type: Application
    Filed: February 15, 2019
    Publication date: August 20, 2020
    Inventors: Cedric LICHTENAU, Reid COPELAND, Petra LEBER, Silvia M. MUELLER, Jonathan D. BRADBURY, Xin GUO
  • Publication number: 20200249982
    Abstract: Instruction interrupt suppression for an overflow condition. An instruction is executed, and a determination is made that an overflow condition occurred. Based on a per-instruction overflow interrupt indicator being set to a defined value, interrupt processing for the overflow condition is performed, and based on the per-instruction overflow interrupt indicator being set to another defined value, the interrupt processing for the overflow condition is bypassed.
    Type: Application
    Filed: February 4, 2019
    Publication date: August 6, 2020
    Inventors: Cedric Lichtenau, Jonathan D. Bradbury, Reid Copeland, Petra Leber
  • Patent number: 10732972
    Abstract: A number of non-overlapping instances of a substring occurring within a string of data elements can be determined through a method that includes partitioning and distributing the string to an ordered list of equal length segments that each have a length greater or equal to L. A substring match within a target segment of the ordered list of segments can be detected by sequentially comparing the substring with each segment of the ordered list of segments. It can be subsequently determined that the target segment contains additional data elements, and a new segment can be generated by clearing L?1 data elements following a position of the substring match in the target segment. An additional substring match can be detected by comparing the substring with the new segment.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: August 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Razvan Peter Figuli, Stefan Payer, Cedric Lichtenau, Petra Leber
  • Publication number: 20200065097
    Abstract: A number of non-overlapping instances of a substring occurring within a string of data elements can be determined through a method that includes partitioning and distributing the string to an ordered list of equal length segments that each have a length greater or equal to L. A substring match within a target segment of the ordered list of segments can be detected by sequentially comparing the substring with each segment of the ordered list of segments. It can be subsequently determined that the target segment contains additional data elements, and a new segment can be generated by clearing L-1 data elements following a position of the substring match in the target segment. An additional substring match can be detected by comparing the substring with the new segment.
    Type: Application
    Filed: August 23, 2018
    Publication date: February 27, 2020
    Inventors: Razvan Peter Figuli, Stefan Payer, Cedric Lichtenau, Petra Leber
  • Patent number: 10416962
    Abstract: Logic is provided for performing decimal and binary floating point arithmetic calculations on first and second operands. The method includes: receiving the first and second operands in packed format; unpacking the first and second operands; swapping the first operand to a fourth operand and the second operand to a third operand, if an exponent of the first operand is less than an exponent of the second operand, otherwise storing the first operand to the third operand and the second operand to the fourth operand; aligning the third operand and the fourth operands based on the exponent difference of the third and fourth operand and a number of leading zeroes of the third operand; performing an add/subtract operation on the aligned third and fourth operands with normalizing and rounding between the operands; and packing the result obtained from the add/subtract.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: September 17, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven R. Carlough, Juergen Haess, Michael Klein, Klaus M. Kroener, Petra Leber, Silvia M. Mueller, Kerstin Schelm
  • Patent number: 10379859
    Abstract: A condition code can depend upon a numerical output of a floating point operation for a processing pipeline. A classification can be determined for the floating point operation of a received instruction. In response to the classification and using condition determination logic, a value can be calculated for the condition code by inferring from data that is available from the processing pipeline before the numerical output is available. The value for the condition code can be provided to branch decision logic of the processing pipeline.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: August 13, 2019
    Assignee: International Business Machines Corporation
    Inventors: Steven R. Carlough, Son T. Dao, Petra Leber, Silvia M. Mueller
  • Patent number: 10379860
    Abstract: A condition code can depend upon a numerical output of a floating point operation for a processing pipeline. A classification can be determined for the floating point operation of a received instruction. In response to the classification and using condition determination logic, a value can be calculated for the condition code by inferring from data that is available from the processing pipeline before the numerical output is available. The value for the condition code can be provided to branch decision logic of the processing pipeline.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: August 13, 2019
    Assignee: International Business Machines Corporation
    Inventors: Steven R. Carlough, Son T. Dao, Petra Leber, Silvia M. Mueller
  • Patent number: 10365892
    Abstract: Processing within a computing environment is facilitated. An operand of an instruction is obtained, which includes decimal floating point data encoded in a compressed format. An operation is performed on the operand absent decompressing a source value of a trailing significand of the decimal floating point data in the compressed format.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: July 30, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven R. Carlough, Petra Leber, Silvia Melitta Mueller, Kerstin Schelm
  • Patent number: 10228910
    Abstract: A circuit is provided which includes arithmetic computation logic configured to add or subtract operands of variable length to produce a result in a sign-magnitude data format. The circuit also includes an overflow detector to provide an overflow signal indicative of whether the result fits within a specified result length l. The overflow detector operates on the operands prior to the arithmetic computation logic producing the result to determine, independent of the result produced by the arithmetic computation logic, whether the result fits within the specified result length l.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: March 12, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Petra Leber, Cedric Lichtenau, Silvia M. Mueller
  • Patent number: 10198302
    Abstract: In an approach for protecting recoding logic in a computing environment, a processor obtains an operand of an instruction in a first data format. A processor converts the operand from the first data format to a second data format. A processor generates a predicted residue of the operand in the second data format, wherein generating the predicted residue of the operand in the second data format comprises: generating a residue of the operand from the first data format.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: February 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Steven R. Carlough, Petra Leber, Daniel Lipetz, Silvia M. Mueller