Abstract: To fabricate an interposer for interfacing waveguides (e.g. optical fiber cables) to transducers, a cavity (410) is formed in a top surface of a substrate. A first layer (520) is formed over the cavity's bottom surface, with one or more gaps in the first layer's top surface. A second layer (3410) is formed in the one or more gaps. The second layer overlaps the first layer. At least part of the first layer is removed to form channels separated from each other by portions of the second layer that are located in the one or more gaps; at least part of the first layer is removed from under the second layer. The second layer portions in the one or more gaps provide one or more spacers in the cavity; these one or more spacers at least partially cover the channels. Waveguides can be placed into the channels.

Abstract: Microelectronic elements and methods of their manufacture are disclosed. A microelectronic element may include a substrate including an opening extending through a semiconductor region of the substrate, a dielectric layer cover a wall of the opening within at least a first portion of the opening, a first metal disposed within the first portion of the opening, a second metal disposed within a second portion of the opening. The second metal may form at least part of a contact of the microelectronic element.

Abstract: An interposer has conductive elements at a first side and terminals at a second side opposite therefrom, for connecting with a microelectronic element and a second component, respectively. The component includes a first element having a thermal expansion coefficient less than 10 ppm/° C., and an insulating second element, with a plurality of openings extending from the second side through the second element towards the first element. A conductive structure extending through the openings in the second element and through the first element electrically connects the terminals with the conductive elements.

Abstract: A method for making an interposer includes forming a plurality of wire bonds bonded to one or more first surfaces of a first element. A dielectric encapsulation is formed contacting an edge surface of the wire bonds which separates adjacent wire bonds from one another. Further processing comprises removing at least portions of the first element, wherein the interposer has first and second opposite sides separated from one another by at least the encapsulation, and the interposer having first contacts and second contacts at the first and second opposite sides, respectively, for electrical connection with first and second components, respectively, the first contacts being electrically connected with the second contacts through the wire bonds.

Abstract: An interposer has conductive elements at a first side and terminals at a second side opposite therefrom, for connecting with a microelectronic element and a second component, respectively. The component includes a first element having a thermal expansion coefficient less than 10 ppm/° C., and an insulating second element, with a plurality of openings extending from the second side through the second element towards the first element. A conductive structure extending through the openings in the second element and through the first element electrically connects the terminals with the conductive elements.

Abstract: Systems and methods for forming MEMS assemblies incorporating getters are described. One such method for forming and bonding to a microelectromechanical systems (MEMS) assembly includes providing a first MEMS wafer including a metal layer on an inner surface and one or more cavities for forming a MEMS component, attaching a MEMS capping wafer, having at least one through hole via, to the inner surface of the first MEMS wafer thereby forming at least one encapsulated MEMs component within the first MEMS wafer, and bonding a wire to the metal layer through an open end of the at least one through hole via.

Abstract: An interconnect element includes a semiconductor or insulating material layer that has a first thickness and defines a first surface; a thermally conductive layer; a plurality of conductive elements; and a dielectric coating. The thermally conductive layer includes a second thickness of at least 10 microns and defines a second surface of the interconnect element. The plurality of conductive elements extend from the first surface of the interconnect element to the second surface of the interconnect element. The dielectric coating is between at least a portion of each conductive element and the thermally conductive layer.

Abstract: Methods of forming a microelectronic assembly and the resulting structures and devices are disclosed herein. In one embodiment, a method of forming a microelectronic assembly includes removing material exposed at portions of a surface of a substrate to form a processed substrate having a plurality of thinned portions separated by integral supporting portions of the processed substrate having a thickness greater than a thickness of the thinned portions, at least some of the thinned portions including a plurality of electrically conductive interconnects extending in a direction of the thicknesses of the thinned portions and exposed at the surface; and removing the supporting portions of the substrate to sever the substrate into a plurality of individual thinned portions, at least some individual thinned portions including the interconnects.

Abstract: A method for making an interconnect element includes depositing a thermally conductive layer on an in-process unit. The in-process unit includes a semiconductor material layer defining a surface and edges surrounding the surface, a plurality of conductive elements, each conductive element having a first portion extending through the semiconductor material layer and a second portion extending from the surface of the semiconductor material layer. Dielectric coatings extend over at least the second portion of each conductive element. The thermally conductive layer is deposited on the in-process unit at a thickness of at least 10 microns so as to overlie a portion of the surface of the semiconductor material layer between the second portions of the conductive elements with the dielectric coatings positioned between the conductive elements and the thermally conductive layer.

Abstract: Methods of processing a device substrate are disclosed herein. In one embodiment, a method of processing a device substrate can include bonding a first surface of a device substrate to a carrier with a polymeric material. The device substrate may have a plurality of first openings extending from the first surface towards a second surface of the device substrate opposite from the first surface. Then, material can be removed at the second surface of the device substrate, wherein at least some of the first openings communicate with the second surface at least one of before or after performing the removal of the material. Then, at least a portion of the polymeric material disposed between the first surface and the carrier substrate can be exposed to a substance through at least some first openings to debond the device substrate from the carrier substrate.

Abstract: Methods of forming a microelectronic assembly and the resulting structures and devices are disclosed herein. In one embodiment, a method of forming a microelectronic assembly includes removing material exposed at portions of a surface of a substrate to form a processed substrate having a plurality of thinned portions separated by integral supporting portions of the processed substrate having a thickness greater than a thickness of the thinned portions, at least some of the thinned portions including a plurality of electrically conductive interconnects extending in a direction of the thicknesses of the thinned portions and exposed at the surface; and removing the supporting portions of the substrate to sever the substrate into a plurality of individual thinned portions, at least some individual thinned portions including the interconnects.

Abstract: Structures and methods of forming the same are disclosed herein. In one embodiment, a structure can comprise a region having first and second oppositely facing surfaces. A barrier region can overlie the region. An alloy region can overlie the barrier region. The alloy region can include a first metal and one or more elements selected from the group consisting of silicon (Si), germanium (Ge), indium (Id), boron (B), arsenic (As), antimony (Sb), tellurium (Te), or cadmium (Cd).

Abstract: A high field of view, low height package and wafer-level packaging process are provided. The top surface of a first wafer has recesses defined by sidewalls, with a reflector, and a floor. The reflector is incident a horizontal light path form an edge-emitting diode on the floor, directing the light path vertically. A second optically diffusing wafer receives the vertically directed light. A vertical ring to surround each recess is wafer-level fabricated on one of the wafers. The vertical ring may have a high aspect ratio to increase light diffusion. The second wafer is connected above the first such that each vertical ring encloses its corresponding recess and such that the light vertically exits the optically diffusing media after spanning the height of the vertical ring. Diode electrical connections are provided for externally controlling the diode. Individual packages are separated by double-dicing the connected wafers between the recesses.

Abstract: Apparatus, systems and methods for use in analyzing discrete reactions at ultra high multiplex with reduced optical noise, and increased system flexibility. Apparatus include substrates having integrated optical components that increase multiplex capability by one or more of increasing density of reaction regions, improving transmission of light to or collection of light from discrete reactions regions. Integrated optical components include reflective optical elements which re-direct illumination light and light emitted from the discrete regions to more efficiently collect emitted light. Particularly preferred applications include single molecule reaction analysis, such as polymerase mediated template dependent nucleic acid synthesis and sequence determination.

Abstract: Structures and methods of forming the same are disclosed herein. In one embodiment, a structure can comprise a region having first and second oppositely facing surfaces. A barrier region can overlie the region. An alloy region can overlie the barrier region. The alloy region can include a first metal and one or more elements selected from the group consisting of silicon (Si), germanium (Ge), indium (Id), boron (B), arsenic (As), antimony (Sb), tellurium (Te), or cadmium (Cd).

Abstract: Processes for making high multiplex arrays for use in analyzing discrete reactions at ultra high multiplex with reduced optical noise, and increased system flexibility. The high multiplex arrays include substrates having integrated optical components that increase multiplex capability by one or more of increasing density of reaction regions, improving transmission of light to or collection of light from discrete reactions regions. Integrated optical components include reflective optical elements which re-direct illumination light and light emitted from the discrete regions to more efficiently collect emitted light. Particularly preferred applications include single molecule reaction analysis, such as polymerase mediated template dependent nucleic acid synthesis and sequence determination.

Abstract: A method of attaching a microelectronic element to a substrate can include aligning the substrate with a microelectronic element, the microelectronic element having a plurality of spaced-apart electrically conductive bumps each including a bond metal, and reflowing the bumps. The bumps can be exposed at a front surface of the microelectronic element. The substrate can have a plurality of spaced-apart recesses extending from a first surface thereof. The recesses can each have at least a portion of one or more inner surfaces that are non-wettable by the bond metal of which the bumps are formed. The reflowing of the bumps can be performed so that at least some of the bond metal of each bump liquefies and flows at least partially into one of the recesses and solidifies therein such that the reflowed bond material in at least some of the recesses mechanically engages the substrate.

Abstract: A high field of view, low height package and wafer-level packaging process are provided. The top surface of a first wafer has recesses defined by sidewalls, with a reflector, and a floor. The reflector is incident a horizontal light path form an edge-emitting diode on the floor, directing the light path vertically. A second optically diffusing wafer receives the vertically directed light. A vertical ring to surround each recess is wafer-level fabricated on one of the wafers. The vertical ring may have a high aspect ratio to increase light diffusion. The second wafer is connected above the first such that each vertical ring encloses its corresponding recess and such that the light vertically exits the optically diffusing media after spanning the height of the vertical ring. Diode electrical connections are provided for externally controlling the diode. Individual packages are separated by double-dicing the connected wafers between the recesses.

Abstract: Structures and methods of forming the same are disclosed herein. In one embodiment, a structure can comprise a region having first and second oppositely facing surfaces. A barrier region can overlie the region. An alloy region can overlie the barrier region. The alloy region can include a first metal and one or more elements selected from the group consisting of silicon (Si), germanium (Ge), indium (Id), boron (B), arsenic (As), antimony (Sb), tellurium (Te), or cadmium (Cd).

Abstract: A method for providing a capping layer configured for an energy assisted magnetic recording (EAMR) head including at least one slider. The method comprises etching a substrate having a top surface using an etch to form a trench in the substrate, the trench having a first surface at a first angle from the top surface and a second surface having a second angle from the top surface. The method further comprises providing a protective coating exposing the second surface and covering the first surface, removing a portion of the substrate including the second surface to form a laser cavity within the substrate configured to fit a laser therein, and providing a reflective layer on the first surface to form a mirror, the cavity and mirror being configured for alignment of the laser to the laser cavity and to the mirror and for bonding the laser to the laser cavity.