Abstract: A differential amplifier comprises: a long tailed pair transistor configuration comprising a differential pair of transistors and a tail transistor; and a replica circuit configured to vary a feedback current in the replica circuit to match a replica voltage to a reference voltage, wherein varying the feedback current in the replica circuit provides a bias voltage to the tail transistor in the long tailed pair which controls a tail current through the tail transistor to determine a common mode voltage in the long tailed pair.

Abstract: A packet-based radio receiver (10) comprises an automatic gain control system (17) and a signal-level detector (18, 19, 20) for monitoring an analog signal derived from radio signals received by the radio receiver. The signal-level detector (18, 19, 20) comprises a binary memory cell (22, 24) and a monitoring system. The monitoring system comprises a comparator (21, 23) arranged to receive a reference voltage at a first input and the analog signal at a second input. The monitoring system is arranged to (i) continuously monitor the voltage of the analog signal, (ii) detect when the monitored signal exceeds the reference voltage, and (iii) store a predetermined binary value in the memory cell (22, 24) in response to such a detection. The automatic gain control system (17) is arranged to control the gain of a variable-gain component (12, 13, 14) of the radio receiver in dependence on the contents of the binary memory cell (22, 24).

Abstract: An operational amplifier comprises: a first amplifier stage 4 comprising a first differential pair of transistors 8, 10 arranged to receive and amplify a differential input signal 18, 20 thereby providing a first differential output signal 22, 24; and a second amplifier stage 6 comprising a second differential pair of transistors 26, 28 arranged to receive and amplify the first differential output signal 22, 24 thereby providing a second differential output signal 38, 40.

Abstract: A start-up circuit arranged to initialize a circuit portion with a zero stable point and a non-zero stable point. The start-up circuit includes: a capacitive voltage divider including a first capacitor and a second capacitor that generate a divider bias voltage at a divider node; a differential amplifier including first and second amplifier inputs and an amplifier output connected to the divider node; a first driver transistor with its gate terminal connected to the divider node, and its drain terminal connected to a first start-up output and the first amplifier input; and a second driver transistor with its gate terminal connected to the divider node, and its drain terminal connected to a second start-up output and the second amplifier input. The differential amplifier controls the divider bias voltage and drives the circuit portion to the non-zero stable point.

Abstract: A start-up circuit (2) arranged to initialise a circuit portion (4) with a zero stable point (200) and a non-zero stable point (202). The start-up circuit comprises: a capacitive voltage divider including a first capacitor (16) and a second capacitor (18) that generate a divider bias voltage at a divider node (48); a differential amplifier including first and second amplifier inputs (20, 22) and an amplifier output connected to the divider node; a first driver transistor (12) with its gate terminal connected to the divider node, and its drain terminal connected to a first start-up output and the first amplifier input; and a second driver transistor (14) with its gate terminal connected to the divider node, and its drain terminal connected to a second start-up output and the second amplifier input. The differential amplifier controls the divider bias voltage and drives the circuit portion to the non-zero stable point.

Abstract: A radio transmitter (4) comprises an encoder (5) that receives one or more variable message bits, and encodes each message bit that has a first value as a predetermined first binary chip sequence and encodes each message bit that has the opposite value as a predetermined second binary chip sequence. The radio transmitter (4) transmits data packets, each comprising (i) a predetermined synchronization portion, comprising one or more instances of the first binary chip sequence, and (ii) a variable data portion, comprising one or more encoded message bits output by the encoder. A radio receiver (9) receives such data packets. It uses the synchronization portion of a received data packet to perform a frequency and/or timing synchronization operation, and then decodes message bits from the data portion of the data packet.

Abstract: A method of digital radio communication between a first device (2) and a second device (8), where each device comprises a radio transmitter (4, 10) and a radio receiver (6, 12), the method comprising: a) said first and second devices (2, 8) establishing a connection using a predetermined protocol having at least one predefined message format; and b) said first and second devices (2, 8) agreeing that in the event of said connection being broken a re-connection may be established using a coding scheme in which at least some bits specified in said predefined message format are represented by a plurality of bits transmitted.

Abstract: A digital radio receiver is adapted to receive radio signals modulated using continuous phase modulation. The receiver includes components for receiving analogue radio signals having various carrier frequencies and a plurality of correlators corresponding to different bit sequences. Each of the plurality of correlators share a common estimator for estimating a frequency offset between the radio signals carrier frequencies and nominal carrier frequencies. The receiver further includes components allowing the estimator to determine which of the correlators produce the most optimal output signal.

Abstract: A differential amplifier comprises: a long tailed pair transistor configuration comprising a differential pair of transistors and a tail transistor; and a replica circuit configured to vary a feedback current in the replica circuit to match a replica voltage to a reference voltage, wherein varying the feedback current in the replica circuit 4 provides a bias voltage to the tail transistor in the long tailed pair which controls a tail current through the tail transistor to determine a common mode voltage in the long tailed pair.

Abstract: An operational amplifier comprises: a first amplifier stage 4 comprising a first differential pair of transistors 8, 10 arranged to receive and amplify a differential input signal 18, 20 thereby providing a first differential output signal 22, 24; and a second amplifier stage 6 comprising a second differential pair of transistors 26, 28 arranged to receive and amplify the first differential output signal 22, 24 thereby providing a second differential output signal 38, 40.

Abstract: A differential comparator has a first input and a second input comprises: first and second transistors arranged as a differential pair connected to the first and second inputs respectively; and a constant current arrangement disposed between said differential pair and a first supply rail; wherein a first path between the first transistor and the constant current arrangement has a different resistance to a second path between the second transistor and the constant current arrangement. Also disclosed is a radio receiver employing such a differential comparator.

Abstract: A packet-based radio receiver (10) comprises an automatic gain control system (17) and a signal-level detector (18, 19, 20) for monitoring an analogue signal derived from radio signals received by the radio receiver. The signal-level detector (18, 19, 20) comprises a binary memory cell (22, 24) and a monitoring system. The monitoring system comprises a comparator (21, 23) arranged to receive a reference voltage at a first input and the analogue signal at a second input. The monitoring system is arranged to (i) continuously monitor the voltage of the analogue signal, (ii) detect when the monitored signal exceeds the reference voltage, and (iii) store a predetermined binary value in the memory cell (22, 24) in response to such a detection. The automatic gain control system (17) is arranged to control the gain of a variable-gain component (12, 13, 14) of the radio receiver in dependence on the contents of the binary memory cell (22, 24).

Abstract: A method of digital radio communication between a first device 2 and a second device 8, where each device comprises a radio transmitter 4, 10 and a radio receiver 6, 12, the method comprising: a) said first and second devices 2, 8 establishing a connection using a predetermined protocol having at least one predefined message format; b) if said connection is subsequently broken, said second device 8 transmitting an advertising message at a first data rate indicating a desire to reconnect; and c) if a reconnection is not established, said second device 8 transmitting a further advertising message at a second data rate indicating a desire to reconnect, wherein said second data rate is lower than the first data rate.

Abstract: A method of digital radio communication between a first device (2) and a second device (8), where each device comprises a radio transmitter (4, 10) and a radio receiver (6, 12), the method comprising: a) said first and second devices (2, 8) establishing a connection using a predetermined protocol having at least one predefined message format; b) if said connection is subsequently broken, said second device (8) transmitting an advertising message at a first data rate indicating a desire to reconnect; and c) if a reconnection is not established, said second device (8) transmitting a further advertising message at a second data rate indicating a desire to reconnect, wherein said second data rate is lower than the first data rate.

Abstract: A radio transmitter (4) comprises an encoder (5) that receives one or more variable message bits, and encodes each message bit that has a first value as a predetermined first binary chip sequence and encodes each message bit that has the opposite value as a predetermined second binary chip sequence. The radio transmitter (4) transmits data packets, each comprising (i) a predetermined synchronisation portion, comprising one or more instances of the first binary chip sequence, and (ii) a variable data portion, comprising one or more encoded message bits output by the encoder. A radio receiver (9) receives such data packets. It uses the synchronisation portion of a received data packet to perform a frequency and/or timing synchronisation operation, and then decodes message bits from the data portion of the data packet.

Abstract: A digital radio receiver 54 is adapted to receive radio signals which are modulated using continuous phase modulation. The receiver comprises means for receiving an analogue radio signal having a carrier frequency, a plurality of correlators 6, 8 each corresponding to a different bit sequence which share a common estimator 4 for estimating a frequency offset between said carrier frequency and a nominal carrier frequency, and means 12 for determining which of said correlators 6, 8 produces a desired output signal.

Abstract: A method of digital radio communication between a first device (2) and a second device (8), where each device comprises a radio transmitter (4, 10) and a radio receiver (6, 12), the method comprising: a) said first and second devices (2, 8) establishing a connection using a predetermined protocol having at least one predefined message format; b) if said connection is subsequently broken, said second device (8) transmitting an advertising message at a first data rate indicating a desire to reconnect; and c) if a reconnection is not established, said second device (8) transmitting a further advertising message at a second data rate indicating a desire to reconnect, wherein said second data rate is lower than the first data rate.

Abstract: A method of digital radio communication between a first device (2) and a second device (8), where each device comprises a radio transmitter (4, 10) and a radio receiver (6, 12), the method comprising: a) said first and second devices (2, 8) establishing a connection using a predetermined protocol having at least one predefined message format; and b) said first and second devices (2, 8) agreeing that in the event of said connection being broken a re-connection may be established using a coding scheme in which at least some bits specified in said predefined message format are represented by a plurality of bits transmitted.

Abstract: Radio transmission apparatus is configured to transmit binary message data in variable-length radio data packets. Each data packet comprises (i) a variable-length data unit and (ii) an error-detecting code for the data unit. The length of the error-detecting code varies between data packets according to a property of each data packet, such as the length of the data unit of the data packet, or a field in the data packet that specifies the length of the error-detecting code.