Patents by Inventor Philip J. Ireland

Philip J. Ireland has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11018097
    Abstract: Guard ring technology is disclosed. In one example, an electronic component guard ring can include a barrier having a first barrier portion and a second barrier portion oriented end to end to block ion diffusion and crack propagation in an electronic component. The guard ring can also include an opening in the barrier between the first and second barrier portions extending between a first side and a second side of the barrier. Associated systems and methods are also disclosed.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: May 25, 2021
    Assignee: Intel Corporation
    Inventors: Hongbin Zhu, Minsoo Lee, Gordon A. Haller, Philip J. Ireland
  • Patent number: 10978386
    Abstract: Microelectronic devices with through-silicon vias and associated methods of manufacturing such devices. One embodiment of a method for forming tungsten through-silicon vias comprising forming an opening having a sidewall such that the opening extends through at least a portion of a substrate on which microelectronic structures have been formed. The method can further include lining the sidewall with a dielectric material, depositing tungsten on the dielectric material such that a cavity extends through at least a portion of the tungsten, and filling the cavity with a polysilicon material.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: April 13, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kyle K. Kirby, Kunal R. Parekh, Philip J. Ireland, Sarah A. Niroumand
  • Publication number: 20200194385
    Abstract: Guard ring technology is disclosed. In one example, an electronic component guard ring can include a barrier having a first barrier portion and a second barrier portion oriented end to end to block ion diffusion and crack propagation in an electronic component. The guard ring can also include an opening in the barrier between the first and second barrier portions extending between a first side and a second side of the barrier. Associated systems and methods are also disclosed.
    Type: Application
    Filed: December 9, 2019
    Publication date: June 18, 2020
    Applicant: Intel Corporation
    Inventors: Hongbin Zhu, Minsoo Lee, Gordon A. Haller, Philip J. Ireland
  • Patent number: 10504859
    Abstract: Guard ring technology is disclosed. In one example, an electronic component guard ring can include a barrier having a first barrier portion and a second barrier portion oriented end to end to block ion diffusion and crack propagation in an electronic component. The guard ring can also include an opening in the barrier between the first and second barrier portions extending between a first side and a second side of the barrier. Associated systems and methods are also disclosed.
    Type: Grant
    Filed: October 1, 2016
    Date of Patent: December 10, 2019
    Assignee: Intel Corporation
    Inventors: Hongbin Zhu, Minsoo Lee, Gordon A. Haller, Philip J. Ireland
  • Patent number: 10121738
    Abstract: Some embodiments include methods of forming interconnects through semiconductor substrates. An opening may be formed to extend partway through a semiconductor substrate, and part of an interconnect may be formed within the opening. Another opening may be formed to extend from a second side of the substrate to the first part of the interconnect, and another part of the interconnect may be formed within such opening. Some embodiments include semiconductor constructions having a first part of a through-substrate interconnect extending partially through a semiconductor substrate from a first side of the substrate; and having a second part of the through-substrate interconnect extending from a second side of the substrate and having multiple separate electrically conductive fingers that all extend to the first part of the interconnect.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: November 6, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Philip J. Ireland
  • Publication number: 20180096955
    Abstract: Guard ring technology is disclosed. In one example, an electronic component guard ring can include a barrier having a first barrier portion and a second barrier portion oriented end to end to block ion diffusion and crack propagation in an electronic component. The guard ring can also include an opening in the barrier between the first and second barrier portions extending between a first side and a second side of the barrier. Associated systems and methods are also disclosed.
    Type: Application
    Filed: October 1, 2016
    Publication date: April 5, 2018
    Applicant: Intel Corporation
    Inventors: Hongbin Zhu, Minsoo Lee, Gordon A. Haller, Philip J. Ireland
  • Publication number: 20170125342
    Abstract: Some embodiments include methods of forming interconnects through semiconductor substrates. An opening may be formed to extend partway through a semiconductor substrate, and part of an interconnect may be formed within the opening. Another opening may be formed to extend from a second side of the substrate to the first part of the interconnect, and another part of the interconnect may be formed within such opening. Some embodiments include semiconductor constructions having a first part of a through-substrate interconnect extending partially through a semiconductor substrate from a first side of the substrate; and having a second part of the through-substrate interconnect extending from a second side of the substrate and having multiple separate electrically conductive fingers that all extend to the first part of the interconnect.
    Type: Application
    Filed: January 16, 2017
    Publication date: May 4, 2017
    Applicant: Micron Technology, Inc.
    Inventors: Alan G. Wood, Philip J. Ireland
  • Patent number: 9583419
    Abstract: Some embodiments include methods of forming interconnects through semiconductor substrates. An opening may be formed to extend partway through a semiconductor substrate, and part of an interconnect may be formed within the opening. Another opening may be formed to extend from a second side of the substrate to the first part of the interconnect, and another part of the interconnect may be formed within such opening. Some embodiments include semiconductor constructions having a first part of a through-substrate interconnect extending partially through a semiconductor substrate from a first side of the substrate; and having a second part of the through-substrate interconnect extending from a second side of the substrate and having multiple separate electrically conductive fingers that all extend to the first part of the interconnect.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: February 28, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Philip J. Ireland
  • Patent number: 9557376
    Abstract: Apparatuses and methods can include a die seal between an integrated circuit region of a die and a periphery of the die. A via chain(s) may be arranged around an inner circumference of the die seal between the die seal and the integrated circuit region and/or around an outer circumference of the die seal between the die seal and the periphery of the die. The via chain may include a plurality of contacts comprised of conductive material and extending through portions of the die. Circuitry may be coupled to an end of the via chain to detect an electrical signal. Additional apparatuses and methods are described.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: January 31, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Charles H. Dennison, Kenneth W. Marr, Deepak Thimmegowda, Philip J. Ireland
  • Publication number: 20160233160
    Abstract: Microelectronic devices with through-silicon vias and associated methods of manufacturing such devices. One embodiment of a method for forming tungsten through-silicon vias comprising forming an opening having a sidewall such that the opening extends through at least a portion of a substrate on which microelectronic structures have been formed. The method can further include lining the sidewall with a dielectric material, depositing tungsten on the dielectric material such that a cavity extends through at least a portion of the tungsten, and filling the cavity with a polysilicon material.
    Type: Application
    Filed: April 19, 2016
    Publication date: August 11, 2016
    Inventors: Kyle K. Kirby, Kunal R. Parekh, Philip J. Ireland, Sarah A. Niroumand
  • Publication number: 20160195581
    Abstract: Apparatuses and methods can include a die seal between an integrated circuit region of a die and a periphery of the die. A via chain(s) may be arranged around an inner circumference of the die seal between the die seal and the integrated circuit region and/or around an outer circumference of the die seal between the die seal and the periphery of the die. The via chain may include a plurality of contacts comprised of conductive material and extending through portions of the die. Circuitry may be coupled to an end of the via chain to detect an electrical signal. Additional apparatuses and methods are described.
    Type: Application
    Filed: March 14, 2016
    Publication date: July 7, 2016
    Inventors: Charles H. Dennison, Kenneth W. Marr, Deepak Thimmegowda, Philip J. Ireland
  • Patent number: 9347985
    Abstract: A via chain testing structure includes: a substrate; a dielectric layer disposed on the substrate; a first via chain disposed on dielectric layer; a second via chain, being disposed on the dielectric on both sides of the first via chain and in thermal proximity with the first via chain; a first heating source disposed under the substrate, for providing thermal heat to the first via chain; and an electrical current source for heating the second via chain so the second via chain acts as a second heating source for the first via chain.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: May 24, 2016
    Assignee: NANYA TECHNOLOGY CORP.
    Inventors: Philip J. Ireland, Wen-Sung Chiang
  • Patent number: 9343362
    Abstract: Microelectronic devices with through-silicon vias and associated methods of manufacturing such devices. One embodiment of a method for forming tungsten through-silicon vias comprising forming an opening having a sidewall such that the opening extends through at least a portion of a substrate on which microelectronic structures have been formed. The method can further include lining the sidewall with a dielectric material, depositing tungsten on the dielectric material such that a cavity extends through at least a portion of the tungsten, and filling the cavity with a polysilicon material.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: May 17, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Kyle K. Kirby, Kunal R. Parekh, Philip J. Ireland, Sarah A. Niroumand
  • Patent number: 9287184
    Abstract: Apparatuses and methods can include a die seal between an integrated circuit region of a die and a periphery of the die. A via chain(s) may be arranged around an inner circumference of the die seal between the die seal and the integrated circuit region and/or around an outer circumference of the die seal between the die seal and the periphery of the die. The via chain may include a plurality of contacts comprised of conductive material and extending through portions of the die. Circuitry may be coupled to an end of the via chain to detect an electrical signal. Additional apparatuses and methods are described.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: March 15, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Charles H. Dennison, Kenneth W. Marr, Deepak Thimmegowda, Philip J. Ireland
  • Publication number: 20150170979
    Abstract: Apparatuses and methods can include a die seal between an integrated circuit region of a die and a periphery of the die. A via chain(s) may be arranged around an inner circumference of the die seal between the die seal and the integrated circuit region and/or around an outer circumference of the die seal between the die seal and the periphery of the die. The via chain may include a plurality of contacts comprised of conductive material and extending through portions of the die. Circuitry may be coupled to an end of the via chain to detect an electrical signal. Additional apparatuses and methods are described.
    Type: Application
    Filed: December 13, 2013
    Publication date: June 18, 2015
    Applicant: Micron Technology, Inc.
    Inventors: Charles H. Dennison, Kenneth W. Marr, Deepak Thimmegowda, Philip J. Ireland
  • Publication number: 20150130029
    Abstract: Some embodiments include methods of forming interconnects through semiconductor substrates. An opening may be formed to extend partway through a semiconductor substrate, and part of an interconnect may be formed within the opening. Another opening may be formed to extend from a second side of the substrate to the first part of the interconnect, and another part of the interconnect may be formed within such opening. Some embodiments include semiconductor constructions having a first part of a through-substrate interconnect extending partially through a semiconductor substrate from a first side of the substrate; and having a second part of the through-substrate interconnect extending from a second side of the substrate and having multiple separate electrically conductive fingers that all extend to the first part of the interconnect.
    Type: Application
    Filed: October 3, 2014
    Publication date: May 14, 2015
    Inventors: Alan G. Wood, Philip J. Ireland
  • Patent number: 8853072
    Abstract: Some embodiments include methods of forming interconnects through semiconductor substrates. An opening may be formed to extend partway through a semiconductor substrate, and part of an interconnect may be formed within the opening. Another opening may be formed to extend from a second side of the substrate to the first part of the interconnect, and another part of the interconnect may be formed within such opening. Some embodiments include semiconductor constructions having a first part of a through-substrate interconnect extending partially through a semiconductor substrate from a first side of the substrate; and having a second part of the through-substrate interconnect extending from a second side of the substrate and having multiple separate electrically conductive fingers that all extend to the first part of the interconnect.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: October 7, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Philip J. Ireland
  • Publication number: 20140287584
    Abstract: Microelectronic devices with through-silicon vias and associated methods of manufacturing such devices. One embodiment of a method for forming tungsten through-silicon vias comprising forming an opening having a sidewall such that the opening extends through at least a portion of a substrate on which microelectronic structures have been formed. The method can further include lining the sidewall with a dielectric material, depositing tungsten on the dielectric material such that a cavity extends through at least a portion of the tungsten, and filling the cavity with a polysilicon material.
    Type: Application
    Filed: December 31, 2013
    Publication date: September 25, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Kyle K. Kirby, Kunal R. Parekh, Philip J. Ireland, Sarah A. Niroumand
  • Patent number: 8753981
    Abstract: Microelectronic devices with through-silicon vias and associated methods of manufacturing such devices. One embodiment of a method for forming tungsten through-silicon vias comprising forming an opening having a sidewall such that the opening extends through at least a portion of a substrate on which microelectronic structures have been formed. The method can further include lining the sidewall with a dielectric material, depositing tungsten on the dielectric material such that a cavity extends through at least a portion of the tungsten, and filling the cavity with a polysilicon material.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: June 17, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kyle K. Kirby, Kunal R. Parekh, Philip J. Ireland, Sarah A. Niroumand
  • Patent number: 8680595
    Abstract: A method and structure are disclosed that are advantageous for aligning a contact plug within a bit line contact corridor (BLCC) to an active area of a DRAM that utilizes an insulated sleeve structure. A sleeve insulator layer is deposited in an opening to protect one or more conductor layers from conductive contacts formed in the opening. The sleeve insulator layer electrically insulates a conductive plug from the conductor layer and self-aligns the BLCC so as to improve contact plug alignment tolerances between the BLCC and the capacitor or conductive components.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: March 25, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Philip J. Ireland, Howard E. Rhodes