Abstract: Applications that use non-volatile random access memory (NVRAM), such as those that apply file system journal writes and database log writes where write operations apply data sequentially over the NVRAM, map the available capacity of the NVRAM in a virtual address space without compromising performance. The NVRAM is segmented into regions with multiple such regions fitting within a volatile RAM element accessible to the application and the NVRAM. One or more regions are loaded in the volatile RAM and reflected in page tables that reference the regions. The page tables are managed on a host computer executing the application. One region space in the volatile RAM is unused and available for transferred information. Mechanisms are provided for dynamically transferring regions and interfacing with the host computer. As the application sequentially accesses information in the stored regions, older regions are removed and new regions loaded from NVRAM to the volatile RAM.

Abstract: An apparatus comprising a memory and a controller. The memory may be configured to (i) implement a cache and (ii) store meta-data. The cache comprises one or more cache windows. Each of the one or more cache windows comprises a plurality of cache-lines configured to store information. Each of the plurality of cache-lines may be associated with meta-data indicating one or more of a dirty state and an invalid state. The controller may be connected to the memory and configured to detect an input/output (I/O) operation directed to a file system. The controller may perform a read-fill based on a hint value when there is a read miss in the cache. The hint value may be based on the application access pattern. The hint value may be passed to a caching layer with a corresponding I/O.

Abstract: Systems and methods maintain cache coherency between storage controllers using input/output virtualization. In one embodiment, a primary storage controller receives write commands over a virtualized interface, stores the write commands in cache memory, tracks a status of the write commands processed from the cache memory, and stores the status in a portion of the cache memory. A backup storage controller includes a backup cache that receives replications of the write commands via direct memory access operations, and stores the replications of the write commands. The primary storage controller makes the status available to a host system. In response to a failure of the primary storage controller, the backup storage synchronizes with the status from the host system, and resumes I/O operations for the logical volume.

Abstract: A first driver may interface with an operating system (OS). A second driver may interface with a plurality of Peripheral Component Interconnect (PCI) devices. The first driver may expose the plurality of PCI devices as a single logical volume to the OS. The OS may boot from the single logical volume that spans the plurality of PCI devices.

Abstract: A block I/O interface for a HBA is disclosed that dynamically loads regions of a SSD of the HBA to a DRAM of the HBA. One embodiment is an apparatus that includes a host system and a HBA. The HBA includes a SSD and DRAM. The host identifies a block I/O read request for the SSD, identifies a region of the SSD that corresponds to the read request, and determines if the region is cached in the DRAM. If the region is cached in the DRAM, then the HBA copies data for the read request to the host memory and a response to the read request utilizes the host memory. If the region is not cached, then the HBA caches the region of the SSD in the DRAM, copies the data for the read request to the host memory, and a response to the read request utilizes the host memory.

Abstract: Applications that use non-volatile random access memory (NVRAM), such as those that apply file system journal writes and database log writes where write operations apply data sequentially over the NVRAM, map the available capacity of the NVRAM in a virtual address space without compromising performance. The NVRAM is segmented into regions with multiple such regions fitting within a volatile RAM element accessible to the application and the NVRAM. One or more regions are loaded in the volatile RAM and reflected in page tables that reference the regions. The page tables are managed on a host computer executing the application. One region space in the volatile RAM is unused and available for transferred information. Mechanisms are provided for dynamically transferring regions and interfacing with the host computer. As the application sequentially accesses information in the stored regions, older regions are removed and new regions loaded from NVRAM to the volatile RAM.

Abstract: An apparatus comprising a memory and a controller. The memory may be configured to (i) implement a cache and (ii) store meta-data. The cache comprises one or more cache windows. Each of the one or more cache windows comprises a plurality of cache-lines configured to store information. Each of the plurality of cache-lines may be associated with meta-data indicating one or more of a dirty state and an invalid state. The controller may be connected to the memory and configured to detect an input/output (I/O) operation directed to a file system. The controller may perform a read-fill based on a hint value when there is a read miss in the cache. The hint value may be based on the application access pattern. The hint value may be passed to a caching layer with a corresponding I/O.

Abstract: A first driver may interface with an operating system (OS). A second driver may interface with a plurality of Peripheral Component Interconnect (PCI) devices. The first driver may expose the plurality of PCI devices as a single logical volume to the OS. The OS may boot from the single logical volume that spans the plurality of PCI devices.

Abstract: An apparatus includes a hybrid memory module, and the hybrid memory module includes volatile memory and non-volatile memory. Data is prearranged in the volatile memory. The data is committed to the non-volatile memory, as prearranged, in a single write operation when a size of the prearranged data reaches a threshold.