Abstract: An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain end diffused link between the buried drift region and the drain contact, and a concurrently formed channel end diffused link between the buried drift region and the channel, where the channel end diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain end diffused link.

Abstract: An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain diffused link, a channel diffused link, and an isolation link which electrically isolated the source, where the isolation diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain diffused link.

Abstract: An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain diffused link, a channel diffused link, and an isolation link which electrically isolated the source, where the isolation diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain diffused link.

Abstract: An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain end diffused link between the buried drift region and the drain contact, and a concurrently formed channel end diffused link between the buried drift region and the channel, where the channel end diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain end diffused link.

Abstract: An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain end diffused link between the buried drift region and the drain contact, and a concurrently formed channel end diffused link between the buried drift region and the channel, where the channel end diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain end diffused link.

Abstract: An integrated circuit and method having a JFET with a buried drift layer and a buried channel in which the buried channel is formed by implanting through segmented implant areas so that the doping density of the buried channel is between 25 percent and 50 percent of the doping density of the buried drift layer.

Abstract: An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain diffused link, a channel diffused link, and an isolation link which electrically isolated the source, where the isolation diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain diffused link.

Abstract: An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain diffused link, a channel diffused link, and an isolation link which electrically isolated the source, where the isolation diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain diffused link.

Abstract: An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain diffused link, a channel diffused link, and an isolation link which electrically isolated the source, where the isolation diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain diffused link.

Abstract: An integrated circuit and method having a JFET with a buried drift layer and a buried channel in which the buried channel is formed by implanting through segmented implant areas so that the doping density of the buried channel is between 25 percent and 50 percent of the doping density of the buried drift layer.

Abstract: An integrated circuit and method having a JFET with a buried drift layer and a buried channel in which the buried channel is formed by implanting through segmented implant areas so that the doping density of the buried channel is between 25 percent and 50 percent of the doping density of the buried drift layer.

Abstract: An integrated circuit and method having a JFET with a buried drift layer and a buried channel in which the buried channel is formed by implanting through segmented implant areas so that the doping density of the buried channel is between 25 percent and 50 percent of the doping density of the buried drift layer.

Abstract: An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain diffused link, a channel diffused link, and an isolation link which electrically isolated the source, where the isolation diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain diffused link.

Abstract: An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain end diffused link between the buried drift region and the drain contact, and a concurrently formed channel end diffused link between the buried drift region and the channel, where the channel end diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain end diffused link.

Abstract: A method of semiconductor fabrication includes providing an unpatterned lightly doped Czochralski bulk silicon substrate (LDCBS substrate) having a concentration of oxygen atoms of at least (?) 1017 atoms/cm3 with a boron doping or n-type doping concentration of between 1×1012 cm?3 and 5×1014 cm?3. Before any oxidization processing, the LDCBS substrate is annealed at a nucleating temperature between 550° C. and 760° C. for a nucleating time that nucleates the oxygen atoms in a sub-surface region of the LDCBS substrate to form oxygen precipitates therefrom. After the annealing, a surface of the LDCBS substrate or an epitaxial layer on the surface of the LDCBS substrate is initially oxidized in an oxidizing ambient at a peak temperature of between 800° C. and 925° C. for a time less than or equal (?) to 30 minutes.

Abstract: Current density in an insulated gate bipolar transistor (L-IGBT) may be increased by adding a second gate, and the corresponding MOS transistors, to the source area, which increases the base current compared to a L-IGBT with a single MOS gate. The current density may be further increased by extending the base of the bipolar transistor in the L-IGBT vertically to the bottom surface of the silicon on insulator (SOI) film in which the L-IGBT is fabricated. Adding a buffer diffused region around the sinks in the source improves the base current spatial uniformity, which improves the safe operating area (SOA) of the L-IGBT. A L-IGBT of either polarity may be formed with the inventive configurations. A method of forming the inventive L-IGBT is also disclosed.

Abstract: Current density in an insulated gate bipolar transistor (L-IGBT) may be increased by adding a second gate, and the corresponding MOS transistors, to the source area, which increases the base current compared to a L-IGBT with a single MOS gate. The current density may be further increased by extending the base of the bipolar transistor in the L-IGBT vertically to the bottom surface of the silicon on insulator (SOI) film in which the L-IGBT is fabricated. Adding a buffer diffused region around the sinks in the source improves the base current spatial uniformity, which improves the safe operating area (SOA) of the L-IGBT. A L-IGBT of either polarity may be formed with the inventive configurations. A method of forming the inventive L-IGBT is also disclosed.