Patents by Inventor Philip M. Freidin
Philip M. Freidin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8467900Abstract: A dispense verification meter for measuring and verifying dispense operations (e.g., actual dispensed volumes) of media dispense systems. The dispense verification meter preferably automatically corrects zero offset drift, preferably samples the flow rate of media being dispensed at a sufficiently high sample rate, and verifies whether the desired dispense operation has been achieved.Type: GrantFiled: May 1, 2012Date of Patent: June 18, 2013Assignee: Malema Engineering CorporationInventor: Philip M. Freidin
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Publication number: 20120211518Abstract: A dispense verification meter for measuring and verifying dispense operations (e.g., actual dispensed volumes) of media dispense systems. The dispense verification meter preferably automatically corrects zero offset drift, preferably samples the flow rate of media being dispensed at a sufficiently high sample rate, and verifies whether the desired dispense operation has been achieved.Type: ApplicationFiled: May 1, 2012Publication date: August 23, 2012Applicant: MALEMA ENGINEERING CORPORATIONInventor: Philip M. Freidin
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Patent number: 8185237Abstract: A dispense verification meter for measuring and verifying dispense operations (e.g., actual dispensed volumes) of media dispense systems. The dispense verification meter preferably automatically corrects zero offset drift, preferably samples the flow rate of media being dispensed at a sufficiently high sample rate, and verifies whether the desired dispense operation has been achieved.Type: GrantFiled: December 28, 2007Date of Patent: May 22, 2012Assignee: Malema Engineering CorporationInventor: Philip M. Freidin
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Publication number: 20090171502Abstract: A dispense verification meter for measuring and verifying dispense operations (e.g., actual dispensed volumes) of media dispense systems. The dispense verification meter preferably automatically corrects zero offset drift, preferably samples the flow rate of media being dispensed at a sufficiently high sample rate, and verifies whether the desired dispense operation has been achieved.Type: ApplicationFiled: December 28, 2007Publication date: July 2, 2009Applicant: Malema Engineering CorporationInventor: Philip M. Freidin
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Patent number: 7187709Abstract: One or more configurable transceivers can be fabricated on an integrated circuit. The transceivers contain various components having options that can be configured by turning configuration memory cells on or off. The integrated circuit may also contain programmable fabric. Other components in the transceivers can have options that are controlled by the programmable fabric. The integrated circuit may also contain one or more processor cores. The processor core and the transceivers can be connected by a plurality of signal paths that pass through the programmable fabric.Type: GrantFiled: March 1, 2002Date of Patent: March 6, 2007Assignee: Xilinx, Inc.Inventors: Suresh M. Menon, Atul V. Ghia, Warren E. Cory, Paul T. Sasaki, Philip M. Freidin, Santiago G. Asuncion, Philip D. Costello, Vasisht M. Vadi, Adebabay M. Bekele, Hare K. Verma
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Patent number: 7111220Abstract: Disclosed are methods and structures for preparing data for transmission over a network. In an embodiment consistent with the OSI network model, transmit and receive CRC generators are moved from the link layer to the physical layer, which frees up valuable programmable logic resources when a programmable logic device is employed to perform the functions of the link layer. The CRC generators of the physical layer comply with a plurality of network communication standards.Type: GrantFiled: March 1, 2002Date of Patent: September 19, 2006Assignee: Xilinx, Inc.Inventors: Paul T. Sasaki, Suresh M. Menon, Atul V. Ghia, Warren E. Cory, Hare K. Verma, Philip M. Freidin
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Patent number: 5995988Abstract: An apparatus for loading configuration information into a programmable integrated circuit (e.g., an FPGA) configurable to perform parallel loading or bit serial loading within the same architecture. The configuration information is presented to the FPGA in data frames of N serial bits each. Each data frame is divided into discrete serial portions having Y bits each (e.g., a data frame comprises N/Y portions). In parallel mode, the portions are loaded into a segmented configuration register, one portion per programming cycle, such that Y bits are loaded into the segmented configuration register in parallel. On each programming clock cycle during parallel loading, all the bits of a data frame portion are simultaneously loaded into the segments of the configuration register (at the first bit position for each segment) such that each segment receives one bit per programming cycle. The bits of the configuration register are then shifted down by one and the cycle repeats for the next data frame portion.Type: GrantFiled: August 10, 1998Date of Patent: November 30, 1999Assignee: Xilinx, Inc.Inventors: Philip M. Freidin, Stephen M. Trimberger, John E. Mahoney, Charles R. Erickson
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Patent number: 5961576Abstract: An apparatus for loading configuration information into a programmable integrated circuit (e.g., an FPGA) configurable to perform parallel loading or bit serial loading within the same architecture. The configuration information is presented to the FPGA in data frames of N serial bits each. Each data frame is divided into discrete serial portions having Y bits each (e.g., a data frame comprises N/Y portions). In parallel mode, the portions are loaded into a segmented configuration register, one portion per programming cycle, such that Y bits are loaded into the segmented configuration register in parallel. On each programming clock cycle during parallel loading, all the bits of a data frame portion are simultaneously loaded into the segments of the configuration register (at the first bit position for each segment) such that each segment receives one bit per programming cycle. The bits of the configuration register are then shifted down by one and the cycle repeats for the next data frame portion.Type: GrantFiled: October 22, 1998Date of Patent: October 5, 1999Assignee: Xilinx, Inc.Inventors: Philip M. Freidin, Stephen M. Trimberger, John E. Mahoney, Charles R. Erickson
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Patent number: 5844829Abstract: An apparatus for loading configuration information into a programmable integrated circuit (e.g., an FPGA) configurable to perform parallel loading or bit serial loading within the same architecture. The configuration information is presented to the FPGA in data frames of N serial bits each. Each data frame is divided into discrete serial portions having Y bits each (e.g., a data frame comprises N/Y portions). In parallel mode, the portions are loaded into a segmented configuration register, one portion per programming cycle, such that Y bits are loaded into the segmented configuration register in parallel. On each programming clock cycle during parallel loading, all the bits of a data frame portion are simultaneously loaded into the segments of the configuration register (at the first bit position for each segment) such that each segment receives one bit per programming cycle. The bits of the configuration register are then shifted down by one and the cycle repeats for the next data frame portion.Type: GrantFiled: December 4, 1997Date of Patent: December 1, 1998Assignee: Xilinx, IncInventors: Philip M. Freidin, Stephen M. Trimberger, John E. Mahoney, Charles R. Erickson
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Patent number: 5742531Abstract: An apparatus for loading configuration information into a programmable integrated circuit (e.g., an FPGA) configurable to perform parallel loading or bit serial loading within the same architecture. The configuration information is presented to the FPGA in data frames of N serial bits each. Each data frame is divided into discrete serial portions having Y bits each (e.g., a data frame comprises N/Y portions). In parallel mode, the portions are loaded into a segmented configuration register, one portion per programming cycle, such that Y bits are loaded into the segmented configuration register in parallel. On each programming clock cycle during parallel loading, all the bits of a data frame portion are simultaneously loaded into the segments of the configuration register (at the first bit position for each segment) such that each segment receives one bit per programming cycle. The bits of the configuration register are then shifted down by one and the cycle repeats for the next data frame portion.Type: GrantFiled: May 3, 1996Date of Patent: April 21, 1998Inventors: Philip M. Freidin, Stephen M. Trimberger, John E. Mahoney, Charles R. Erickson
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Patent number: 5726584Abstract: A virtual high density architecture having shared memory cells for a programmable integrated circuit (IC) is provided. The architecture includes logic modules, a configuration memory unit (CMU), and a global interconnect memory (GIMU) unit. A logic cycle is divided into a number of time intervals. For each time interval, the CMU outputs information to configure the logic modules and the interconnect structure to realize an individual circuit stage of a circuit. Input and output data pertinent to this individual stage are retrieved from and stored in the GIMU based on addressing information generated from the CMU for each time interval. The CMU continuously reprograms the logic modules and interconnect structure for each time interval to realize different stages of the circuit while information used between stages is stored in the GIMU.Type: GrantFiled: March 18, 1996Date of Patent: March 10, 1998Assignee: Xilinx, Inc.Inventor: Philip M. Freidin
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Patent number: 5661660Abstract: Logic is represented in a schematic capture program as a generic symbol. The generic symbol represents a single underlying logic circuit, thereby decreasing library space. The generic symbol includes a configuration memory which is represented on the symbol by a plurality of pins. The generic symbol is configured by indicating the logic signals placed on the plurality of pins. In this manner, the generic symbol significantly increases the design choices available to the end user. Moreover, the generic symbol allows access to the underlying logic of the circuit via the selected bit pattern, thereby advantageously permitting the end user to perform functional simulation within the schematic environment. In one embodiment, a plug symbol is provided to schematically connect to the generic symbol. This plug symbol represents a predetermined pattern of bits, thereby significantly simplifying configuring the logic in the schematic capture program.Type: GrantFiled: May 9, 1994Date of Patent: August 26, 1997Assignee: Xilinx, Inc.Inventor: Philip M. Freidin
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Patent number: 5646564Abstract: A controlled delay path inserts a selected delay into a clock distribution circuit to create a total clock delay that is equal to an integer number of clock cycles relative to a reference input clock signal or which produces a selected phase relationship to the reference clock signal. The delay path correction of the invention is particularly useful in circuits having a wide range of possible system clock frequencies or having programmable routing of clock signals, and therefore a wide range of operating delays. A reference input clock signal is directed to a range of selectable voltage controlled delay elements by a phase detector that receives the reference input clock signal and a feedback signal, and that produces an error voltage which adjusts the voltage controlled delay elements to produce an output clock signal. Additional selectable delays may be included that create offset options and allow selection of a leading, lagging, or in-phase reference input clock/output clock relationship.Type: GrantFiled: April 12, 1996Date of Patent: July 8, 1997Assignee: Xilinx, Inc.Inventors: Charles R. Erickson, Philip M. Freidin, Kerry M. Pierce
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Patent number: 5631577Abstract: A configurable logic block (CLB) in the dual port mode uses one address to write the same information in a first RAM and a second RAM. The input signals provided to the second function generator can be used to read, independently from and even asynchronously with, the write operation, thereby dramatically increasing the speed of applications using the two sets of RAM. A CLB in the synchronous mode latches the appropriate address and data signals, and generates a strobed write enable signal. The strobed signal is self-timed, i.e. the write operation is fully automatic, thereby ensuring that a write operation occurs within one clock cycle.Type: GrantFiled: June 21, 1996Date of Patent: May 20, 1997Assignee: Xilinx, Inc.Inventors: Philip M. Freidin, Edmond Y. Cheung, Charles R. Erickson, Tsung-Lu Syu
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Patent number: 5598424Abstract: The present invention provides a means and method of generating a long error checking polynomial remainder having the ability to detect errors with high reliability and inserting only a subset of the polynomial remainder periodically into a data stream, then at the receiving end recalculating the polynomial remainder and checking the inserted subset for errors. The polynomial has the property that the current remainder value is a function of all data previously transmitted in a transmission session. The subset transmitted also preferably has this property. A longer subset of the polynomial remainder, or the full polynomial remainder, may be inserted less frequently, and is preferably sent and tested at the end of the transmission session. Both serial and parallel data streams may be checked.Type: GrantFiled: June 14, 1994Date of Patent: January 28, 1997Assignee: Xilinx, Inc.Inventors: Charles R. Erickson, Philip M. Freidin, William A. Wilkie
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Patent number: 5566123Abstract: A configurable logic block (CLB) in the dual port mode uses one address to write the same information in a first RAM and a second RAM. The input signals provided to the second function generator can be used to read, independently from and even asynchronously with, the write operation, thereby dramatically increasing the speed of applications using the two sets of RAM. A CLB in the synchronous mode latches the appropriate address and data signals, and generates a strobed write enable signal. The strobed signal is self-timed, i.e. the write operation is fully automatic, thereby ensuring that a write operation occurs within one clock cycle.Type: GrantFiled: February 10, 1995Date of Patent: October 15, 1996Assignee: Xilinx, Inc.Inventors: Philip M. Freidin, Edmond Y. Cheung, Charles R. Erickson, Tsung-Lu Syu
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Patent number: 5414377Abstract: A logic block for a field programmable logic device which is of the type using memory bits in a look-up table to provide any function of several inputs, and which uses additional memory bits to control aspects of the configuration, achieves a smaller size by replacing memory bits which control some configuration choices of the logic block with multiplexers which alternately select a default configuration or allow the look-up table memory bits to control the configuration. Thus the memory bits perform an alternate function of serving as a look-up table to generate a function, and controlling gates such as multiplexers, XOR gates or AND gates to generate a function.Type: GrantFiled: October 18, 1994Date of Patent: May 9, 1995Assignee: Xilinx, Inc.Inventor: Philip M. Freidin
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Patent number: 5410194Abstract: According to the present invention hardware is provided in a user configurable logic integrated circuit chip to allow a user to select multiple storage functions such as D, T, JK, to receive multiple input signals and generate a storage input signal using a function such as OR or MUX, along with parallel load and asynchronous load options. A relatively small hardware area can offer these functions, which are commonly used, and can leave general purpose logic for other more complex functions, thus increasing the amount of logic which a user may implement in a given silicon area.Type: GrantFiled: August 11, 1993Date of Patent: April 25, 1995Assignee: Xilinx, Inc.Inventors: Philip M. Freidin, Charles R. Erickson
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Patent number: 5321704Abstract: The present invention provides a means and method of generating a long error checking polynomial remainder having the ability to detect errors with high reliability and inserting only a subset of the polynomial remainder periodically into a data stream, then at the receiving end recalculating the polynomial remainder and checking the inserted subset for errors. The polynomial has the property that the current remainder value is a function of all data previously transmitted in a transmission session. The subset transmitted also preferably has this property. A longer subset of the polynomial remainder, or the full polynomial remainder, may be inserted less frequently, and is preferably sent and tested at the end of the transmission session.Type: GrantFiled: January 16, 1991Date of Patent: June 14, 1994Assignee: Xilinx, Inc.Inventors: Charles R. Erickson, Philip M. Freidin
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Patent number: 4926323Abstract: A streamlined instruction processor processes data in response to a program composed of prespecified instructions in pipeline cycles. The processor comprises an instruction fetch unit, including an instruction interface adapted for connection to an instruction memory and for fetching instructions from the instruction memory. The instruction fetch unit includes an instruction prefetch buffer coupled to the instruction interface for buffering a sequence of instructions supplied to the instruction interface. A branch target cache is coupled with the prefetch buffer for storing sets of instructions retrieved from a corresponding set of locations in the instruction memory, having sequential instruction addresses. The first instruction in each such set is a branch target instruction in the program.In addition, an execution unit including a data interface adapted for connection to the data memory, executes the instructions in pipeline cycles.Type: GrantFiled: March 3, 1988Date of Patent: May 15, 1990Assignee: Advanced Micro Devices, Inc.Inventors: Gigy Baror, Brian W. Case, Rod G. Fleck, Philip M. Freidin, Smeeta Gupta, William M. Johnson, Cheng-Gang Kong, Ole H. Moller, Timothy A. Olson, David I. Sorensen