Abstract: A memory module performs a memory readiness test, and reports results to a host system. The memory module initializes a status register with an initial ready time value and a memory readiness status. The memory module conducts the memory readiness test, and while conducting the memory readiness test, estimates a new ready time based on the progress of the memory readiness test. The memory module updates the ready time value in the status register based on the new ready time. After finishing the memory readiness test, the memory module updates the memory readiness status in the status register.

Abstract: An electronic device includes a processor that executes a guest operating system; a memory having a guest portion that is reserved for storing data and information to be accessed by the guest operating system; and an input-output memory management unit (IOMMU). The IOMMU performs operations for signaling an interrupt to the guest operating system. For these operations, the IOMMU acquires, from an entry in an interrupt remapping table associated with the guest operating system, a location in a virtual advanced programmable interrupt controller (APIC) backing page for the guest operating system in the guest portion of the memory. The IOMMU then writes information about the interrupt to the location in the virtual APIC backing page. The IOMMU next communicates an indication of the interrupt to the guest operating system.

Abstract: A networked input/output memory management unit (IOMMU) includes a plurality of IOMMUs. The networked IOMMU receives a memory access request that includes a domain physical address generated by a first address translation layer. The networked IOMMU selectively translates the domain physical address into a physical address in a system memory using one of the plurality of IOMMUs that is selected based on a type of a device that generated the memory access request. In some cases, the networked IOMMU is connected to a graphics processing unit (GPU), at least one peripheral device, and the memory. The networked IOMMU includes a command queue to receive the memory access requests, a primary IOMMU to selectively translate the domain physical address in memory access requests from the GPU, and a secondary IOMMU to translate the domain physical address in memory requests from the peripheral device.

Abstract: An electronic device includes a processor that executes a guest operating system, an input-output memory management unit (IOMMU), and a main memory that stores an IOMMU backing store. The IOMMU backing store includes a separate copy of a set of IOMMU memory-mapped input-output (MMIO) registers for each guest operating system in a set of supported guest operating systems. The IOMMU receives, from the guest operating system, a communication that accesses data in a given IOMMU MMIO register. The IOMMU then performs a corresponding access of the data in a copy of the given IOMMU MMIO register in the IOMMU backing store associated with the guest operating system.

Abstract: A method of managing memory access includes receiving, at an input output memory management unit, a memory access request from a device. The memory access request includes a virtual steering tag associate associated with a virtual machine. The method further includes translating the virtual steering tag to a physical steering tag directing memory access of a cache memory associated with a processor core of a plurality of processor cores. The virtual machine is implemented on the processor core. The method also includes accessing the cache memory to implement the memory access request.

Abstract: An electronic device includes a processor that executes a guest operating system; a memory having a guest portion that is reserved for storing data and information to be accessed by the guest operating system; and an input-output memory management unit (IOMMU). The IOMMU writes, in the guest portion, information into guest buffers and/or logs used for communicating information from the IOMMU to the guest operating system. The IOMMU also reads, from the guest portion, information in guest buffers and/or logs used for communicating information from the guest operating system to the IOMMU.

Abstract: An electronic device includes a processor that executes a guest operating system, an input-output memory management unit (IOMMU), and a main memory that stores an IOMMU backing store. The IOMMU backing store includes a separate copy of a set of IOMMU memory-mapped input-output (MMIO) registers for each guest operating system in a set of supported guest operating systems. The IOMMU receives, from the guest operating system, a communication that accesses data in a given IOMMU MMIO register. The IOMMU then performs a corresponding access of the data in a copy of the given IOMMU MMIO register in the IOMMU backing store associated with the guest operating system.

Abstract: A processing system includes a plurality of input/output (I/O) devices representing a plurality of I/O resources. Each I/O resource has at least one corresponding memory mapped I/O (MMIO) address range. A trap handler detects a write request targeting a configuration space of an identified I/O resource of the plurality of I/O resources and, responsive to determining the identified I/O resource is a protected I/O resource, selectively blocks the write request from further processing by the processing system based on whether the write request would change an MMIO address decoding of the identified I/O resource.

Abstract: An electronic device includes a processor that executes a guest operating system and a hypervisor, an input-output (IO) device, and an input-output memory management unit (IOMMU). The IOMMU handles communications between the IOMMU and the guest operating system by: replacing, in communications received from the guest operating system, guest domain identifiers (domainIDs) with corresponding host domainIDs and/or guest device identifiers (deviceIDs) with corresponding host deviceIDs before further processing the communications; replacing, in communications received from the IO device, host deviceIDs with guest deviceIDs before providing the communications to the guest operating system; and placing, into communications generated in the IOMMU and destined for the guest operating system, guest domainIDs and/or guest deviceIDs before providing the communications to the guest operating system. The IOMMU handles the communications without intervention by the hypervisor.

Abstract: An alignment bracket for a roller blind, comprising a base and a roller tube support securable to the base. First and second coupling members on the base and roller tube support permit an adjustment of the alignment of the roller tube support, and the end of a roller tube mounted thereon, relative to the base. Also provided is a blind fabric alignment device for a roller tube of a multi-tube roller blind. The alignment device comprises a drive coupling body securable to an end of a roller tube of the blind, a driven member mounted to the drive coupling body, a torque transfer mechanism secured to the driven member, and an adjuster. The torque transfer mechanism transfers rotational torque from the driven member to the drive coupling body through the adjuster. The adjuster permits an alteration of the rotational position of the driven member relative to the drive coupling body.

Abstract: An alignment bracket for a roller blind, comprising a base and a roller tube support securable to the base. First and second coupling members on the base and roller tube support permit an adjustment of the alignment of the roller tube support, and the end of a roller tube mounted thereon, relative to the base. Also provided is a blind fabric alignment device for a roller tube of a multi-tube roller blind. The alignment device comprises a drive coupling body securable to an end of a roller tube of the blind, a driven member mounted to the drive coupling body, a torque transfer mechanism secured to the driven member, and an adjuster. The torque transfer mechanism transfers rotational torque from the driven member to the drive coupling body through the adjuster. The adjuster permits an alteration of the rotational position of the driven member relative to the drive coupling body.

Abstract: Systems, methods, and port controller designs employ a light-weight memory protocol. A light-weight memory protocol controller is selectively coupled to a Cache Coherent Interconnect for Accelerators (CCIX) port. Over an on-chip interconnect fabric, the light-weight protocol controller receives memory access requests from a processor and, in response, transmits associated memory access requests to an external memory through the CCIX port using only a proper subset of CCIX protocol memory transactions types including non-cacheable transactions and non-snooping transactions. The light-weight memory protocol controller is selectively uncoupled from the CCIX port and a remote coherent slave controller is coupled in its place. The remote coherent slave controller receives memory access requests and, in response, transmits associated memory access requests to a memory module through the CCIX port using cacheable CCIX protocol memory transaction types.

Abstract: Systems, apparatuses, and methods for aligning active and idle phases of components in a computing system are disclosed. A computing system includes components that can be forced into an active or idle phase and components that cannot be forced into an active or idle phase. The system implements schemes for aligning the active and idle phases of the components within the system. For example, a timer starts counting when a processor and memory subsystem go from a low power state to an operational state. If the amount of time spent by the processor and memory subsystems in the operational state without transitioning to the low power state exceeds a threshold, the system forces active-to-idle and idle-to-active phase transitions of components in the system in order to cause a realignment of active and idle phases of the various components within the system.

Abstract: An apparatus includes a graphics processing unit (GPU) and a frame buffer. The frame buffer is coupled to the GPU. Based upon initialization of a virtual function, a plurality of pages are mapped into a virtual frame buffer. The plurality of pages are mapped into the virtual frame buffer by using a graphics input/output memory management unit (GIOMMU) and an associated page table.

Abstract: A torque transfer coupler for a roller blind. The torque transfer coupler has a central body securable to an electric motor and includes one or more torque transfer elements engaging the interior of the blind's roller tube. The coupler includes an anti-slip member having one or more resilient portions having a rest position and a deflected position. When, in their rest positions the resilient portions have a dimension larger than the cross sectional area of the roller tube. When in their deflected positions and received within the roller tube the resilient portions engage the interior surface of the roller tube resisting the withdrawal of the torque transfer coupler, and the electric motor secured thereto, from the interior of the roller tube.

Abstract: A system has a processor including a plurality of processor cores, a memory controller, and an input-output memory management unit. The plurality of processor cores implements a plurality of virtual machines. The system further has a device in communication with the input-output memory management unit, the device including a bus controller, a device memory controller, an encryption module, a device memory, and a computational resource. The device is to implement a plurality of virtual functions. The device provides a device memory access request from a virtual function to the device memory controller. The virtual function is associated with a virtual function identifier. The device is to determine an encryption key associated with the virtual function, decrypt information stored at the device memory using the encryption key, and provide the decrypted information in a processor memory access request to the processor.

Abstract: A method of managing memory access includes receiving, at an input output memory management unit, a memory access request from a device. The memory access request includes a virtual steering tag associate associated with a virtual machine. The method further includes translating the virtual steering tag to a physical steering tag directing memory access of a cache memory associated with a processor core of a plurality of processor cores. The virtual machine is implemented on the processor core. The method also includes accessing the cache memory to implement the memory access request.

Abstract: Bus protocol features are provided for chaining memory access requests on a high speed interconnect bus, allowing for reduced signaling overhead. Multiple memory request messages are received over a bus. A first message has a source identifier, a target identifier, a first address, and first payload data. The first payload data is stored in a memory at locations indicated by the first address. Within a selected second one of the request messages, a chaining indicator is received associated with the first request message and second payload data. The second request message does not include an address. Based on the chaining indicator, a second address for which memory access is requested is calculated based on the first address. The second payload data is stored in the memory at locations indicated by the second address.

Abstract: A Management Component Transport Protocol platform management subsystem includes an internal bridge, a first segment group, and a second segment group. The first segment group is coupled to the internal bridge. The second segment group is coupled to the internal bridge and the first segment group. The first segment group has a first plurality of Peripheral Component Interconnect Express (PCIe)-based buses. The second segment group has a second plurality of PCIe-based buses, wherein based on an identification (ID)-routed packet from the first segment group to the second segment group, the internal bridge routes the ID-routed packet to the second segment group.

Abstract: A system-on-chip (SOC), includes a memory, a partition access module coupled to the memory, a partition requesting unit coupled to the partition access module, and a first input-output (IO) device coupled to the partition access module. The partition access module creates a first partition of the SOC. The first partition includes a first portion of a first processor, the first IO device, and a first portion of the memory. Based upon a partition request, the partition access module repartitions the SOC to create a dynamic partition. The dynamic partition includes the first portion of the first processor, the first input-output (IO) device, the first portion of the memory, and a second IO device not included in the first partition.