Abstract: A memory system having a memory controller and a memory. The memory comprises one or more daisy chains of self timed memory chips. An address/command word is chained through a daisy chain of memory chips and is handled by one of the memory chips in the daisy chain of memory chips. Data to be written to a memory chip is sent as part of the address/command word, or is transferred on an outgoing data bus chain. Data read from a memory chip is transferred on an incoming data bus chain. Access timing on a memory chip is determined by a self time block on the memory chip.

Abstract: A method and apparatus are provided for identifying product tampering. A mechanical fastening screw, a sleeve and a movable follower disk are arranged to show evidence of tampering. The movable follower disk is received within a cavity defined by the sleeve. The sleeve includes a channel and a final resting slot defined within a sleeve wall. The movable follower disk includes compressible spring followers slideably received within the channel when the mechanical fastening screw is inserted. If the screw is removed, the compressible spring followers engage the final resting slot to indicate tampering. Electrical detection of the compressible spring followers engaging the final resting slot is used to identify tampering.

Abstract: A method, structures and computer program product are provided for implementing enhanced wiring capability for electronic laminate packages. Electronic package physical design data are received. Instances of line width and space limit violations in the electronic package physical design data are identified. The identified instances of line width and space limit violations are evaluated using predefined qualified options and tolerance limitations and the electronic package physical design data are modified to optimize shapes to replace the instances of line width and space limit violations.

Abstract: A method of testing and an embedded probe-enabling socket are provided for implementing debug and testing functions. The socket includes an integral probe structure enabling Top Side of the Module (TSM) signal probing. The socket includes a substrate with a topside including a plurality of probe pads. A TSM socket frame includes a plurality of probe pins electrically connecting to respective probe pads on the substrate topside. The probe pins are electrically connected with a respective signal to be monitored.

Abstract: A method and structure are provided to control common mode impedance in fan-out regions for printed circuit board applications. A differential pair transmission line includes a narrow signal trace portion in the fan-out region and a wider signal trace portion outside of the fan-out region. A dielectric material separates the differential pair transmission line from a reference power plane. A thickness of the narrow signal trace is increased and a thickness of the dielectric material is correspondingly decreased in the fan-out region.

Abstract: A method and stiffener-embedded waveguide structure are provided for implementing enhanced data transfer for printed circuit board applications. At least one microwave channel is defined within a stiffener. The microwave channel provides a high frequency path for data transfers. Use of the waveguide channel in the stiffener for data transfers can replace or supplement otherwise required transmission paths in an associated printed circuit board.

Abstract: A socket assembly with incorporated memory structure is provided. A chip carrier socket assembly includes dual stage clamping actuation. A first clamping actuation stage provides clamping force for ball grid array (BGA) contact pads and a second clamping actuation stage provides clamping force for a thermal interface. The first clamping actuation stage provides clamping force proximate to a perimeter of a carrier where a plurality of BGA contact pads are located. The second clamping actuation stage provides clamping force generally centrally of the chip carrier socket assembly for thermal interface actuation.

Abstract: Methods and apparatus are provided for implementing silicon wafer chip carrier passive devices including customized silicon capacitors and resistors mounted directly on a module or carrier package. A plurality of system design inputs is received for a package arrangement. A respective physical design is generated for customized passive devices, a logic chip, and a chip carrier. Silicon devices are fabricated utilizing the generated respective physical design for customized passive devices and the logic chip and a carrier package is fabricated. The fabricated silicon devices are assembled on the carrier package.

Abstract: A method and structure are provided for implementing a column attach coupled noise suppressor for a solder column structure of the type used to join a substrate to a circuit card. The electrical noise suppressor structure includes a plurality of elongated through openings that are arranged in a predefined pattern. The elongated through openings have electrically conductive sidewalls and are electrically connected together. The predefined pattern of the elongated, electrically conductive through openings corresponds to a layout of solder columns. The solder columns are attached at one end to either a substrate or a circuit card and are inserted through the elongated through openings of the electrical noise suppressor structure, spaced apart from the electrically conductive sidewalls. Then the solder columns are attached at the other end to the other one of the substrate or circuit card.

Abstract: A method and structures are provided for implementing an impedance-controlled coupled noise suppressor for a differential interface solder column array used to join a substrate to a circuit card. The impedance-controlled coupled noise suppressor structure includes a plurality of elongated through openings that are arranged in a predefined pattern with one or more of the through openings receiving a differential signal pair of solder columns. The elongated through openings have electrically conductive sidewalls and are electrically connected together. The predefined pattern of the elongated, electrically conductive through openings corresponds to a layout of solder columns. The solder columns are attached at opposite ends to a substrate and a circuit card. An electrical connection is provided between the impedance-controlled coupled noise suppressor structure and an image return current path of the circuit card.

Abstract: A method and structure are provided to control common mode impedance in fan-out regions for printed circuit board applications. A differential pair transmission line includes a narrow signal trace portion in the fan-out region and a wider signal trace portion outside of the fan-out region. A dielectric material separates the differential pair transmission line from a reference power plane. A thickness of the narrow signal trace is increased and a thickness of the dielectric material is correspondingly decreased in the fan-out region.

Abstract: A method and apparatus are provided for implementing direct attenuation loss measurement in an electronic package. A sinusoidal voltage source signal of a selected frequency is coupled to an embedded transmission line test structure in the electronic package. Receive circuitry is coupled to the transmission line test structure for detecting amplitude of a received sinusoidal voltage source signal to identify attenuation loss through the transmission line test structure. An identified attenuation loss of the transmission line test structure is compared with a threshold value for verifying acceptable attenuation of the electronic package transmission line test structure.

Abstract: A method and a probe structure are provided for implementing multiple signals probing of a printed circuit board. A probe structure is formed on an outside surface of the printed circuit board. A resistor is electrically connected with an associated via with a signal to be monitored. A path to a predefined probe location for monitoring the signal is defined from the resistor using the probe structure.

Abstract: A method and apparatus are provided for implementing automated electronic package transmission line characteristic impedance verification. A sinusoidal voltage source is coupled to a transmission line test structure for generating a selected frequency. Impedance measuring circuitry is coupled to the transmission line test structure for measuring an input impedance with an open-circuit termination and a short-circuit termination. Characteristic impedance calculation circuitry is coupled to the impedance measuring circuitry receiving the input impedance measured values for the open-circuit termination and the short-circuit termination for calculating characteristic impedance. Logic circuitry is coupled to the characteristic impedance calculation circuitry for comparing the calculated characteristic impedance with threshold values for verifying acceptable electronic package transmission line characteristic impedance.

Abstract: Methods and apparatus are provided for implementing silicon wafer chip carrier passive devices including customized silicon capacitors and resistors mounted directly on a module or carrier package. A plurality of system design inputs is received for a package arrangement. A respective physical design is generated for customized passive devices, a logic chip, and a chip carrier. Silicon devices are fabricated utilizing the generated respective physical design for customized passive devices and the logic chip and a carrier package is fabricated. The fabricated silicon devices are assembled on the carrier package.

Abstract: The present invention provides apparatus and methods to eliminate a required “dead cycle” or “living cycle” during transfer of control from a first source terminated driver to a second source terminated driver on a bidirectional signaling conductor. On a last bus cycle on which the first driver drives the signaling conductor, the first driver stops driving and goes into a high impedance state respondent to detection that the first driver current has become lower than a predetermined current or that a voltage at the output of the first driver has become within a predetermined voltage difference of a target voltage. The second driver, knowing that the first driver will be switched to a high impedance state, can assume control of the signaling wire and drive a signal on the signaling conductor shortly after receipt of the signal from the first driver.

Abstract: Methods and apparatus are disclosed for improved via utilization on printed wiring boards (PWB). A via in a PWB typically transfers a single electrical signal from one signal plane to another wiring plane on the PWB. The present invention provides for more than a single signal to be transferred through a single via having a conducting wall. The conducting wall of the via is divided into more than one conducting portion, each portion capable of conducting a signal from one signal plane to another signal plane.

Abstract: A method and structure are provided for implementing enhanced differential signal trace routing in a printed circuit board. The structure includes a differential signal trace pair and a differential pair via arrangement including a pair of vias. The pair of vias is coupled to the differential signal trace pair for routing the differential signal trace pair between first and second layers of the PCB. The vias are laterally offset by a predefined spacing sharing overlapping clearance holes and are diagonally oriented to allow minimal separation of the differential signal trace pair and matched signal trace lengths of the differential signal trace pair.

Abstract: A method and embedded bus bar structure are provided for implementing power distribution in an electronic system. A stiffener includes an embedded power bus bar structure for distributing power. The embedded power bus bar structure has a predefined pattern within a selected area of the stiffener. The selected area is separated from at least one predefined area. A printed circuit board is mounted to the stiffener and electrically connected to the embedded power bus bar structure. The embedded power bus bar structure can include multiple spaced apart power bus bars, enabling the power distribution of multiple voltage levels. The predefined pattern of the embedded power bus bar structure within the selected area of the stiffener is separated from each predefined site for a Land Grid Array (LGA).