Patents by Inventor Philippe Boivin
Philippe Boivin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11957067Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.Type: GrantFiled: May 24, 2021Date of Patent: April 9, 2024Assignees: STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS (ROUSSET) SASInventors: Philippe Boivin, Simon Jeannot
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Publication number: 20240081160Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.Type: ApplicationFiled: November 10, 2023Publication date: March 7, 2024Applicants: STMicroelectronics (Crolles 2) SAS, STMICROELECTRONICS (ROUSSET) SASInventors: Philippe BOIVIN, Simon JEANNOT
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Patent number: 11882707Abstract: The disclosure relates to integrated circuits including one or more rows of transistors and methods of forming rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a first semiconductor layer having a plurality of first conduction regions, a second semiconductor layer having a second conduction region, a common base between the first semiconductor layer and the second semiconductor layer, and a plurality of insulator walls extending in a first direction. The first conduction regions are separated from one another by the insulator walls. The integrated circuit further includes an insulating trench extending in a second direction and in contact with each of the bipolar transistors of the row of bipolar transistors. A conductive layer is coupled to the base, and the conductive layer extends through the insulator walls and extends at least partially into the insulating trench.Type: GrantFiled: December 22, 2021Date of Patent: January 23, 2024Assignee: STMicroelectro (Rousset) SASInventor: Philippe Boivin
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Patent number: 11875847Abstract: Memory devices such as phase change memory (PCM) devices utilizing Ovonic Threshold Switching (OTS) selectors may be used to fill the gap between dynamic random-access memory (DRAM) and mass storage and may be incorporated in high-end microcontrollers. Since the programming efficiency and reading phase efficiency of such devices is directly linked to the leakage current of the OTS selector as well as sneak-path management, a sense amplifier disclosed herein generates an auto-reference that takes into account the leakage currents of unselected cells and includes a regulation loop to compensate for voltage drop due to read current sensing. This auto-referenced sense amplifier, built utilizing the principle of charge-sharing, may be designed on a 28 nm fully depleted silicon-on-insulator (FDSOI) technology, provides robust performance for a wide range of sneak-path currents and consequently for a large range of memory array sizes, and is therefore suitable for use in embedded memory in high-end microcontroller.Type: GrantFiled: February 16, 2022Date of Patent: January 16, 2024Assignees: Universite D'Aix Marseille, Centre National De La Recherche Scientifique, STMicroelectro (Crolles 2) SAS, STMicroelectronics (Rousset) SASInventors: Jean-Michel Portal, Vincenzo Della Marca, Jean-Pierre Walder, Julien Gasquez, Philippe Boivin
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Patent number: 11818901Abstract: The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions.Type: GrantFiled: September 29, 2021Date of Patent: November 14, 2023Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SASInventors: Philippe Boivin, Jean Jacques Fagot, Emmanuel Petitprez, Emeline Souchier, Olivier Weber
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Patent number: 11800821Abstract: The present disclosure concerns a phase-change memory manufacturing method and a phase-change memory device. The method includes forming a first insulating layer in cavities located vertically in line with strips of phase-change material, and anisotropically etching the portions of the first insulating layer located at the bottom of the cavities; and a phase-change memory device including a first insulating layer against lateral walls of cavities located vertically in line with strips of phase-change material.Type: GrantFiled: July 1, 2022Date of Patent: October 24, 2023Assignees: STMicroelectronics (Crolles 2) SAS, STMICROELECTRONICS (ROUSSET) SASInventors: Philippe Boivin, Daniel Benoit, Remy Berthelon
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Publication number: 20230263082Abstract: An integrated circuit includes a substrate with an active area, a first insulating layer, a second insulating layer, and a phase-change material. The integrated circuit further includes a heating element in an L-shape, with a long side in direct physical contact with the phase-change material and a short side in direct physical contact with a via. The heating element is surrounded by first, second, and third insulating spacers, with the first insulating spacer having a planar first sidewall in contact with the long side of the heating element, a convex second sidewall, and a planar bottom face in contact with the short side of the heating element. The second and third insulating spacers are in direct contact with the first insulating spacer and the long side of the heating element.Type: ApplicationFiled: April 3, 2023Publication date: August 17, 2023Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Rousset) SASInventors: Franck ARNAUD, David GALPIN, Stephane ZOLL, Olivier HINSINGER, Laurent FAVENNEC, Jean-Pierre ODDOU, Lucile BROUSSOUS, Philippe BOIVIN, Olivier WEBER, Philippe BRUN, Pierre MORIN
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Publication number: 20230260574Abstract: Memory devices such as phase change memory (PCM) devices utilizing Ovonic Threshold Switching (OTS) selectors may be used to fill the gap between dynamic random-access memory (DRAM) and mass storage and may be incorporated in high-end microcontrollers. Since the programming efficiency and reading phase efficiency of such devices is directly linked to the leakage current of the OTS selector as well as sneak-path management, a sense amplifier disclosed herein generates an auto-reference that takes into account the leakage currents of unselected cells and includes a regulation loop to compensate for voltage drop due to read current sensing. This auto-referenced sense amplifier, built utilizing the principle of charge-sharing, may be designed on a 28 nm fully depleted silicon-on-insulator (FDSOI) technology, provides robust performance for a wide range of sneak-path currents and consequently for a large range of memory array sizes, and is therefore suitable for use in embedded memory in high-end microcontroller.Type: ApplicationFiled: February 16, 2022Publication date: August 17, 2023Applicants: Universite D'Aix Marseille, Centre National De La Recherche Scientifique, STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SASInventors: Jean-Michel PORTAL, Vincenzo DELLA MARCA, Jean-Pierre WALDER, Julien GASQUEZ, Philippe BOIVIN
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Publication number: 20230240082Abstract: The disclosure concerns a resistive memory cell, including a stack of a selector, of a resistive element, and of a layer of phase-change material, the selector having no physical contact with the phase-change material. In one embodiment, the selector is an ovonic threshold switch formed on a conductive track of a metallization level.Type: ApplicationFiled: March 31, 2023Publication date: July 27, 2023Applicant: STMicroelectronics (Rousset) SASInventor: Philippe BOIVIN
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Patent number: 11653582Abstract: An electronic chip includes memory cells made of a phase-change material and a transistor. First and second vias extend from the transistor through an intermediate insulating layer to a same height. A first metal level including a first interconnection track in contact with the first via is located over the intermediate insulating layer. A heating element for heating the phase-change material is located on the second via, and the phase-change material is located on the heating element. A second metal level including a second interconnection track is located above the phase-change material. A third via extends from the phase-change material to the second interconnection track.Type: GrantFiled: November 8, 2018Date of Patent: May 16, 2023Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Rousset) SASInventors: Franck Arnaud, David Galpin, Stephane Zoll, Olivier Hinsinger, Laurent Favennec, Jean-Pierre Oddou, Lucile Broussous, Philippe Boivin, Olivier Weber, Philippe Brun, Pierre Morin
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Patent number: 11637144Abstract: The disclosure concerns a resistive memory cell, including a stack of a selector, of a resistive element, and of a layer of phase-change material, the selector having no physical contact with the phase-change material. In one embodiment, the selector is an ovonic threshold switch formed on a conductive track of a metallization level.Type: GrantFiled: August 23, 2021Date of Patent: April 25, 2023Inventor: Philippe Boivin
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Publication number: 20220367497Abstract: The integrated circuit of a non-volatile memory of the electrically erasable and programmable type includes memory cells, each memory cell having a state transistor including a gate structure comprising a control gate and a floating gate disposed on a face of a semiconductor well, as well as a source region and a drain region in the semiconductor well. The drain region includes a first capacitive implant region positioned predominantly under the gate structure and a lightly doped region positioned predominantly outside the gate structure. The source region includes a second capacitive implant region positioned predominantly outside the gate structure, the source region not including a lightly doped region.Type: ApplicationFiled: May 2, 2022Publication date: November 17, 2022Applicant: STMicroelectronics (Rousset) SASInventors: Francois TAILLIET, Roberto SIMOLA, Philippe BOIVIN
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Publication number: 20220336736Abstract: The present disclosure concerns a phase-change memory manufacturing method and a phase-change memory device. The method includes forming a first insulating layer in cavities located vertically in line with strips of phase-change material, and anisotropically etching the portions of the first insulating layer located at the bottom of the cavities; and a phase-change memory device including a first insulating layer against lateral walls of cavities located vertically in line with strips of phase-change material.Type: ApplicationFiled: July 1, 2022Publication date: October 20, 2022Applicants: STMicroelectronics (Crolles 2) SAS, STMICROELECTRONICS (ROUSSET) SASInventors: Philippe BOIVIN, Daniel BENOIT, Remy BERTHELON
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Patent number: 11411177Abstract: The present disclosure concerns a phase-change memory manufacturing method and a phase-change memory device. The method includes forming a first insulating layer in cavities located vertically in line with strips of phase-change material, and anisotropically etching the portions of the first insulating layer located at the bottom of the cavities; and a phase-change memory device including a first insulating layer against lateral walls of cavities located vertically in line with strips of phase-change material.Type: GrantFiled: May 20, 2020Date of Patent: August 9, 2022Assignees: STMicroelectronics (Crolles 2) SAS, STMICROELECTRONICS (ROUSSET) SASInventors: Philippe Boivin, Daniel Benoit, Remy Berthelon
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Patent number: 11329067Abstract: An electronic integrated circuit chip includes a first transistor arranged inside and on top of a solid substrate, a second transistor arranged inside and on top of a layer of semiconductor material on insulator having a first thickness, and a third transistor arranged inside and on top of a layer of semiconductor material on insulator having a second thickness. The second thickness is greater than the first thickness. The solid substrate extends underneath the layers of semiconductor material and is insulated from those layers by the insulator.Type: GrantFiled: June 11, 2020Date of Patent: May 10, 2022Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SASInventors: Jean-Jacques Fagot, Philippe Boivin, Franck Arnaud
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Publication number: 20220140232Abstract: The present description concerns a device including phase-change memory cells, each memory cell including a first resistive element in lateral contact with a second element made of a phase-change material.Type: ApplicationFiled: October 21, 2021Publication date: May 5, 2022Applicants: STMicroelectronics (Crolles 2) SAS, STMICROELECTRONICS (ROUSSET) SASInventors: Philippe BOIVIN, Roberto SIMOLA, Yohann MOUSTAPHA-RABAULT
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Publication number: 20220140233Abstract: The present description concerns a device including phase-change memory cells, each memory cell including a first resistive element in lateral contact with a second element made of a phase-change material.Type: ApplicationFiled: October 22, 2021Publication date: May 5, 2022Applicant: STMICROELECTRONICS (ROUSSET) SASInventor: Philippe BOIVIN
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Publication number: 20220130904Abstract: The present description concerns a method of forming a track in a first layer, including a) forming a cavity in the first layer; b) totally filling the cavity with a first material; and c) partially removing the first material from the upper portion of the cavity, to form the track made of the first material.Type: ApplicationFiled: October 21, 2021Publication date: April 28, 2022Applicant: STMICROELECTRONICS (ROUSSET) SASInventor: Philippe BOIVIN
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Publication number: 20220123119Abstract: A memory transistor for a non-volatile memory cell includes a source region and a drain region implanted in a semiconductor substrate. The source region is spaced from the drain region. A double gate region for the memory transistor extends at least partly in depth in the semiconductor substrate between the source region and the drain region and further extends beyond this source region and this drain region. The memory cell further includes a selection transistor having a gate region that partially extends over the double gate region for the memory transistor.Type: ApplicationFiled: October 18, 2021Publication date: April 21, 2022Applicant: STMicroelectronics (Rousset) SASInventors: Christian RIVERO, Philippe BOIVIN, Francois TAILLIET, Roberto SIMOLA
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Publication number: 20220115441Abstract: The disclosure relates to integrated circuits including one or more rows of transistors and methods of forming rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a first semiconductor layer having a plurality of first conduction regions, a second semiconductor layer having a second conduction region, a common base between the first semiconductor layer and the second semiconductor layer, and a plurality of insulator walls extending in a first direction. The first conduction regions are separated from one another by the insulator walls. The integrated circuit further includes an insulating trench extending in a second direction and in contact with each of the bipolar transistors of the row of bipolar transistors. A conductive layer is coupled to the base, and the conductive layer extends through the insulator walls and extends at least partially into the insulating trench.Type: ApplicationFiled: December 22, 2021Publication date: April 14, 2022Applicant: STMicroelectronics (Rousset) SASInventor: Philippe BOIVIN