Patents by Inventor Phillip A. Fischer

Phillip A. Fischer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10439602
    Abstract: In accordance with aspects of the present invention, a power control circuit includes a MAIN window comparator circuit providing a MAIN signal; an AUX window comparator circuit providing an AUX signal; a state machine receiving the MAIN signal and the AUX signal; a MAIN slew circuit coupled to drive a MAIN switch, the MAIN switch coupled between MAIN and an output; an AUX slew circuit coupled to drive an AUX switch, the AUX switch coupled between AUX and the output; wherein the state machine operates to continuously activate either the MAIN switch or the AUX switch according to the MAIN signal and the AUX signal such that the output is continuously coupled to either a MAIN input or an AUX input with minimum disruption to output voltage, input and output capacitance inrush currents or reverse conduction. What really makes the circuit unique is it is combined with an adjustable forward biased rectification circuit for each channel of MAIN and AUX.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: October 8, 2019
    Assignee: ProGrAnalog Corporation
    Inventors: Roger Beeston, David F. Baretich, Phillip Fischer, Quincy Chan, Bob Fite
  • Patent number: 10126791
    Abstract: In accordance with aspects of the present invention, a programmable power management integrated circuit is presented. An integrated circuit can include a plurality of cells, each cell including at least one driver for a switchable element; and a switch matrix and controller coupled to the plurality of cells, the switch matrix and controller being programmable to configure at least one power channel, each power channel including at least one cell of the plurality of cells. A method of providing a power management system using the integrated circuit includes receiving power requirements corresponding to a target device; providing implementation options to achieve the power requirements; selecting a solution from the implementation options; generating a programming file for a power management integrated circuit, and generating a printed circuit board design for the power management integrated circuit.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: November 13, 2018
    Assignee: PROGRANALOG CORP.
    Inventors: Roger Beeston, Phillip Fischer, Robert Fite
  • Patent number: 6593621
    Abstract: A lateral DMOS transistor incorporates one or more enhancement schemes for improving the breakdown voltage characteristics and ruggedness of the transistor. In one embodiment, the drain region of the lateral DMOS transistor is separated from the body region by a first distance in the rectilinear region necessary to achieve a first breakdown voltage, and separated by a second distance in the curved region necessary to achieve at least the first breakdown voltage, the second distance being greater than the first distance. In another embodiment, the gate partially overlies the field oxide region by a third distance in the rectilinear region and by a fourth distance in the curved region, the fourth distance being greater than the third distance. The enhancement schemes optimize the breakdown voltage characteristics and ruggedness of the lateral DMOS transistor in both the rectilinear and curved regions.
    Type: Grant
    Filed: August 23, 2001
    Date of Patent: July 15, 2003
    Assignee: Micrel, Inc.
    Inventors: Hideaki Tsuchiko, Bruce Lee Inn, Marty Garnett, Phillip Fischer
  • Publication number: 20030038316
    Abstract: A lateral DMOS transistor incorporates one or more enhancement schemes for improving the breakdown voltage characteristics and ruggedness of the transistor. In one embodiment, the drain region of the lateral DMOS transistor is separated from the body region by a first distance in the rectilinear region necessary to achieve a first breakdown voltage, and separated by a second distance in the curved region necessary to achieve at least the first breakdown voltage, the second distance being greater than the first distance. In another embodiment, the gate partially overlies the field oxide region by a third distance in the rectilinear region and by a fourth distance in the curved region, the fourth distance being greater than the third distance. The enhancement schemes optimize the breakdown voltage characteristics and ruggedness of the lateral DMOS transistor in both the rectilinear and curved regions.
    Type: Application
    Filed: August 23, 2001
    Publication date: February 27, 2003
    Inventors: Hideaki Tsuchiko, Bruce Lee Inn, Marty Garnett, Phillip Fischer
  • Patent number: 5653173
    Abstract: A magnetic levitated vehicle, including a linear rotor connected thereto, runs on a tubular track having a circular cross-section and a tubular linear induction motor stator mounted therein. The rotor is movably mounted within the stator and the vehicle is positioned above the track. The rotor is connected to the vehicle by a riser extending through longitudinal slots of the track and stator, and by an actuator mechanism, which includes a transversely curved saddle movably connected to drive members, for enabling the vehicle to be banked at curve sections of the tubular track. Further, vehicle banking is also accomplished by constructing the track and stator with the slots laterally offset at the curved sections of the track.
    Type: Grant
    Filed: February 10, 1995
    Date of Patent: August 5, 1997
    Inventor: Phillip A. Fischer