Abstract: In one embodiment, methods for making semiconductor devices are disclosed.

Abstract: Methods of forming a semiconductor package. Implementations include providing a leadframe, coupling a semiconductor die or an electronic component to the leadframe, and encapsulating at least a portion of the semiconductor die or the electronic component using a mold compound leaving two or more leads of the leadframe exposed. The method may also include coating the two or more leads of the leadframe with an electrically conductive layer. The method may include fully electrically and physically singulating one or more tie bars between two or more leads of the leadframe, a lead of the two or more leads and a leadframe flag, or any combination thereof. The method may also include singulating the leadframe to form one or more semiconductor packages.

Abstract: In one embodiment, methods for making semiconductor devices are disclosed.

Abstract: In one embodiment, methods for making semiconductor devices are disclosed.

Abstract: Methods of forming a semiconductor package. Implementations include providing a leadframe, coupling a semiconductor die or an electronic component to the leadframe, and encapsulating at least a portion of the semiconductor die or the electronic component using a mold compound leaving two or more leads of the leadframe exposed. The method may also include coating the two or more leads of the leadframe with an electrically conductive layer. The method may include fully electrically and physically singulating one or more tie bars between two or more leads of the leadframe, a lead of the two or more leads and a leadframe flag, or any combination thereof. The method may also include singulating the leadframe to form one or more semiconductor packages.

Abstract: Methods of forming a semiconductor package. Implementations include providing a leadframe, coupling a semiconductor die or an electronic component to the leadframe, and encapsulating at least a portion of the semiconductor die or the electronic component using a mold compound leaving two or more leads of the leadframe exposed. The method may also include coating the two or more leads of the leadframe with an electrically conductive layer. The method may include fully electrically and physically singulating one or more tie bars between two or more leads of the leadframe, a lead of the two or more leads and a leadframe flag, or any combination thereof. The method may also include singulating the leadframe to form one or more semiconductor packages.

Abstract: Methods of forming a semiconductor package. Implementations include providing a leadframe, coupling a semiconductor die or an electronic component to the leadframe, and encapsulating at least a portion of the semiconductor die or the electronic component using a mold compound leaving two or more leads of the leadframe exposed. The method may also include coating the two or more leads of the leadframe with an electrically conductive layer. The method may include fully electrically and physically singulating one or more tie bars between two or more leads of the leadframe, a lead of the two or more leads and a leadframe flag, or any combination thereof. The method may also include singulating the leadframe to form one or more semiconductor packages.

Abstract: A method for plating package leads, in some embodiments, comprises: providing a package having a lead electrically coupled to a tie bar; singulating said lead; electroplating said singulated lead using the tie bar; and singulating said tie bar.

Abstract: Methods of forming a semiconductor package. Implementations include providing a leadframe, coupling a semiconductor die or an electronic component to the leadframe, and encapsulating at least a portion of the semiconductor die or the electronic component using a mold compound leaving two or more leads of the leadframe exposed. The method may also include coating the two or more leads of the leadframe with an electrically conductive layer. The method may include fully electrically and physically singulating one or more tie bars between two or more leads of the leadframe, a lead of the two or more leads and a leadframe flag or any combination thereof. The method may also include singulating the leadframe to form one or more semiconductor packages.

Abstract: In accordance with an embodiment, a semiconductor component includes a support having a first device receiving structure, a second device receiving structure, a first lead and a second lead. A first semiconductor chip is coupled to the first device receiving structure and a second semiconductor chip is coupled to the first semiconductor chip and the second device receiving structure. The first semiconductor chip is configured from a silicon semiconductor material and has a gate bond pad, a source bond pad, and a drain bond pad, and the second semiconductor chip is configured from a gallium nitride semiconductor chip and has a gate bond pad, a source bond pad, and a drain bond pad. In accordance with another embodiment, a method for manufacturing a semiconductor component includes coupling a first semiconductor chip to a support and coupling a second semiconductor chip to the support.

Abstract: In one embodiment, methods for making semiconductor devices are disclosed.

Abstract: In accordance with an embodiment, a semiconductor component includes a support having a first device receiving structure, a second device receiving structure, a first lead and a second lead. A first semiconductor chip is coupled to the first device receiving structure and a second semiconductor chip is coupled to the first semiconductor chip and the second device receiving structure. The first semiconductor chip is configured from a silicon semiconductor material and has a gate bond pad, a source bond pad, and a drain bond pad, and the second semiconductor chip is configured from a gallium nitride semiconductor chip and has a gate bond pad, a source bond pad, and a drain bond pad. In accordance with another embodiment, a method for manufacturing a semiconductor component includes coupling a first semiconductor chip to a support and coupling a second semiconductor chip to the support.

Abstract: Methods of forming a semiconductor package. Implementations include providing a leadframe, coupling a semiconductor die or an electronic component to the leadframe, and encapsulating at least a portion of the semiconductor die or the electronic component using a mold compound leaving two or more leads of the leadframe exposed. The method may also include coating the two or more leads of the leadframe with an electrically conductive layer. The method may include fully electrically and physically singulating one or more tie bars between two or more leads of the leadframe, a lead of the two or more leads and a leadframe flag, or any combination thereof. The method may also include singulating the leadframe to form one or more semiconductor packages.

Abstract: In one embodiment, a semiconductor package includes a first and a second die flag, wherein the first and second die flags are separated by a gap. First and second metal oxide semiconductor field effect transistor (MOSFET) die are on the first and the second die flags, respectively. A power control integrated circuit (IC) is stacked on top of at least one of the first or the second MOSFET die. A mold compound is encapsulating the power control IC, the first and second MOSFET die, and the first and second die flags.

Abstract: A semiconductor component having wettable leadframe lead surfaces and a method of manufacture. A leadframe having leadframe leads is embedded in a mold compound. The mold compound is separated to form singulated semiconductor components. A portion of at least one leadframe lead is exposed and an electrically conductive material is formed on the exposed portion using one of a vibratory plating device or a spouted bed electroplating device.

Abstract: In one embodiment, a semiconductor package includes a first and a second die flag, wherein the first and second die flags are separated by a gap. First and second metal oxide semiconductor field effect transistor (MOSFET) die are on the first and the second die flags, respectively. A power control integrated circuit (IC) is stacked on top of at least one of the first or the second MOSFET die. A mold compound is encapsulating the power control IC, the first and second MOSFET die, and the first and second die flags.

Abstract: A semiconductor component having wettable leadframe lead surfaces and a method of manufacture. A leadframe having leadframe leads is embedded in a mold compound. A portion of at least one leadframe lead is exposed and an electrically conductive material is formed on the exposed portion. The mold compound is separated to form singulated semiconductor components.

Abstract: In one embodiment, a leadframe for a semiconductor package includes a source connection area for one transistor and a drain connection point for a second transistor, and a common connection for using a connection clip to couple a drain of the first transistor to a source of the second transistor and to the common connection.

Abstract: In one embodiment, a leadframe for a semiconductor package includes a source connection area for one transistor and a drain connection point for a second transistor, and a common connection for using a connection clip to couple a drain of the first transistor to a source of the second transistor and to the common connection.

Abstract: A semiconductor component and a method for manufacturing the semiconductor component, wherein the semiconductor component is configured to permit the determination of circuit parameters. A high side FET has a gate terminal coupled to an output terminal of a high side gate drive circuit, a drain terminal coupled for receiving an input voltage, and a source terminal coupled to the drain terminal of a low side FET. The gate terminal of the low side FET is coupled to the output terminal of low side drive circuit and the source terminal of the low side FET is coupled for receiving a source of operating potential. The high side gate drive circuit has a bias terminal coupled for receiving a floating potential where the bias terminal is electrically isolated or decoupled from the commonly connected source and drain terminals of the high side FET and the low side FET, respectively.