Patents by Inventor Phillip J. Restle

Phillip J. Restle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170031383
    Abstract: A pulse-drive resonant clock with on-the fly mode changing provides robust operation in a resonant clock distribution network, in particular for processor circuits having a dynamically-varied operating frequency. The clock drivers for the resonant clock distribution network include a pulse width control circuit having selectable operating modes corresponding to multiple clocking modes of the resonant clock distribution network. The pulse width control circuit includes a delay line that has a selectable delay length to provide pulse enable signals that control the pulse widths of the clock drivers in a sector of the resonant clock distribution network. The delay line responds to a mode control signal so that at least one pulse width of the output is changed from a first pulse width to a second pulse width without generating half-cycles with a pulse width narrower than the first or second pulse width.
    Type: Application
    Filed: July 31, 2015
    Publication date: February 2, 2017
    Inventors: Thomas J. Bucelot, Robert L. Franch, Phillip J. Restle, David Wen-Hao Shan, Christos Vezyrtzis
  • Publication number: 20170031384
    Abstract: A pulse-drive resonant clock with on-the fly mode changing provides robust operation in a resonant clock distribution network, in particular for processor circuits having a dynamically-varied operating frequency. The clock drivers for the resonant clock distribution network include a pulse width control circuit having selectable operating modes corresponding to multiple clocking modes of the resonant clock distribution network. The pulse width control circuit includes a delay line that has a selectable delay length to provide pulse enable signals that control the pulse widths of the clock drivers in a sector of the resonant clock distribution network. The delay line responds to a mode control signal so that at least one pulse width of the output is changed from a first pulse width to a second pulse width without generating half-cycles with a pulse width narrower than the first or second pulse width.
    Type: Application
    Filed: August 18, 2015
    Publication date: February 2, 2017
    Inventors: Thomas J. Bucelot, Robert L. Franch, Phillip J. Restle, David Wen-Hao Shan, Christos Vezyrtzis
  • Patent number: 9494968
    Abstract: A method for adjusting clock skew in a network is disclosed. A model is fit to a first clock input signal received at a first receiver of the network and to a second clock input signal received at a second receiver of the network to obtain a fitted model. A first response signal is simulated using the fitted model and the first clock input signal and a second response signal is simulated using the fitted model and the second clock input signal. A time difference is determined between the simulated first response signal and the simulated second response signal. A parameter of at least one of the network clock network, the first receiver and the second receiver is altered to adjust the determined time difference.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: November 15, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Phillip J. Restle, James D. Warnock
  • Publication number: 20160211833
    Abstract: A method for providing a stitchable clock mesh, a dual operation mode system, and a method for providing a master clock stratum are, in turn, provided for a 3D chip stack having two or more strata. The method for providing a stitchable clock mesh includes providing, by at least one clock mesh disposed on each stratum and having multiple sectors, a global clock signal to various chip locations. The method further includes collecting, by mesh data sensors on each stratum, mesh data for the at least one mesh. The mesh data includes measured functional data and measured performance data for a current system configuration. The method also includes selectively performing, by joining circuitry, a segmentation operation or a joining operation on the least one mesh or one or more portions thereof responsive to the mesh data and the current system configuration selectable from a plurality of system target configurations.
    Type: Application
    Filed: March 30, 2016
    Publication date: July 21, 2016
  • Patent number: 9348357
    Abstract: A stitchable clock mesh, a dual operation mode method, and a master clock stratum are provided for a 3D chip stack. The stitchable clock mesh includes at least one clock mesh, on each of the two or more strata, having a plurality of sectors for providing a global clock signal. The stitchable clock mesh further includes mesh data sensors, on each of the two or more strata, for collecting mesh data for the at least one mesh. The mesh data includes measured functional data and measured performance data for a current system configuration. The stitchable clock mesh further includes mesh segmentation and joining circuitry for selectively performing a segmentation operation or a joining operation on the least one mesh or one or more portions thereof responsive to the mesh data and the current system configuration selectable from a plurality of system target configurations.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: May 24, 2016
  • Publication number: 20160105177
    Abstract: A clock driver is provided. The clock driver includes a multi-stage delay cell having an input, a positive pulse driving branch, a negative pulse driving branch, and an output. The input is for receiving an original version of a reference clock signal input to the clock driver and used to generate a global clock signal. The output is connected to the positive pulse driving branch and the negative pulse driving branch. The clock driver further includes a pulse generator having positive and negative pulse generator portions respectively connected to outputs of the positive and negative pulse driving branches. The pulse generator generates, at any given time, one of a positive pulse and a negative pulse responsive to a positive pulse enable signal and a negative pulse enable signal, respectively, and the original version of the reference clock signal input to the clock driver without modification.
    Type: Application
    Filed: December 17, 2015
    Publication date: April 14, 2016
    Inventors: ADITYA BANSAL, THOMAS J. BUCELOT, ALAN J. DRAKE, PHILLIP J. RESTLE, DAVID W. SHAN, MRIGANK SHARAD
  • Patent number: 9276563
    Abstract: A clock driver and corresponding method are provided. The clock driver includes a multi-stage delay cell having logic circuitry and a plurality of serially connected delay elements. An input of the delay elements receives an original version of a reference clock signal input to the clock driver and used to generate a global clock signal. An output of the delay elements connects to positive and negative pulse driving branches formed from the logic circuitry. The clock driver further includes a pulse generator forming positive and negative pulse generator portions respectively connected to outputs of the positive and negative pulse driving branches. The pulse generator generates, at any given time, one of a positive pulse and a negative pulse responsive to a positive pulse enable signal and a negative pulse enable signal, respectively, and the original version of the reference clock signal input to the clock driver without modification.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: March 1, 2016
    Assignee: International Business Machines Corporation
    Inventors: Aditya Bansal, Thomas J. Bucelot, Alan J. Drake, Phillip J. Restle, David W. Shan, Mrigank Sharad
  • Patent number: 9268886
    Abstract: Recycling energy in a clock distribution network is provided. A method includes creating a resonant clocking circuit including a clock grid. The method further includes providing resonant structures distributed in the clock grid. The method further includes providing switches that control the resonant structures to switch between a non-resonant mode and a resonant mode. The method further includes determining a switch size that minimizes power consumption of the resonant clocking circuit by iteratively increasing sizes of the switches and, for each iterative increase in size, determining power consumed by the resonant clocking circuit.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: February 23, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jason D. Hibbeler, William R. Reohr, Phillip J. Restle
  • Patent number: 9231603
    Abstract: There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. The clock distribution circuit includes, on each of the two or more strata, phase detectors, a logic circuit, and a phase de-skewing element. Each phase detector has a respective output for providing phase information relating to a phase difference between two of the global clocks signals on respective different ones of the two or more strata. The logic circuit is connected to the respective outputs of the phase detectors for determining a phase adjustment plan for a given one of the two or more strata upon which the logic circuit is located responsive to the phase information. The phase de-skewing element is for adjusting a clock skew of a same stratum located one of the two of the global clock signals responsive to the phase adjustment plan.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: January 5, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yong Liu, Liang-Teck Pang, Phillip J. Restle
  • Publication number: 20150378388
    Abstract: A stitchable clock mesh, a dual operation mode method, and a master clock stratum are provided for a 3D chip stack. The stitchable clock mesh includes at least one clock mesh, on each of the two or more strata, having a plurality of sectors for providing a global clock signal. The stitchable clock mesh further includes mesh data sensors, on each of the two or more strata, for collecting mesh data for the at least one mesh. The mesh data includes measured functional data and measured performance data for a current system configuration. The stitchable clock mesh further includes mesh segmentation and joining circuitry for selectively performing a segmentation operation or a joining operation on the least one mesh or one or more portions thereof responsive to the mesh data and the current system configuration selectable from a plurality of system target configurations.
    Type: Application
    Filed: June 30, 2014
    Publication date: December 31, 2015
  • Publication number: 20150365076
    Abstract: A clock driver and corresponding method are provided. The clock driver includes a multi-stage delay cell having logic circuitry and a plurality of serially connected delay elements. An input of the delay elements receives an original version of a reference clock signal input to the clock driver and used to generate a global clock signal. An output of the delay elements connects to positive and negative pulse driving branches formed from the logic circuitry. The clock driver further includes a pulse generator forming positive and negative pulse generator portions respectively connected to outputs of the positive and negative pulse driving branches. The pulse generator generates, at any given time, one of a positive pulse and a negative pulse responsive to a positive pulse enable signal and a negative pulse enable signal, respectively, and the original version of the reference clock signal input to the clock driver without modification.
    Type: Application
    Filed: June 13, 2014
    Publication date: December 17, 2015
    Inventors: ADITYA BANSAL, THOMAS J. BUCELOT, ALAN J. DRAKE, PHILLIP J. RESTLE, DAVID W. SHAN, MRIGANK SHARAD
  • Publication number: 20150280722
    Abstract: There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. The clock distribution circuit includes, on each of the two or more strata, phase detectors, a logic circuit, and a phase de-skewing element. Each phase detector has a respective output for providing phase information relating to a phase difference between two of the global clocks signals on respective different ones of the two or more strata. The logic circuit is connected to the respective outputs of the phase detectors for determining a phase adjustment plan for a given one of the two or more strata upon which the logic circuit is located responsive to the phase information. The phase de-skewing element is for adjusting a clock skew of a same stratum located one of the two of the global clock signals responsive to the phase adjustment plan.
    Type: Application
    Filed: March 31, 2014
    Publication date: October 1, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yong Liu, Liang-Teck Pang, Phillip J. Restle
  • Publication number: 20150234422
    Abstract: A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit and a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid. The tunable sector buffer is configured to set latency and slew rate of the clock signal based on an identified resonant or non-resonant mode.
    Type: Application
    Filed: May 7, 2015
    Publication date: August 20, 2015
    Inventors: Thomas J. Bucelot, Alan J. Drake, Robert A. Groves, Jason D. Hibbeler, Yong I. Kim, Liang-Teck Pang, William R. Reohr, Phillip J. Restle, Michael G.R. Thomson
  • Patent number: 9058130
    Abstract: A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit and a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid. The tunable sector buffer is configured to set latency and slew rate of the clock signal based on an identified resonant or non-resonant mode.
    Type: Grant
    Filed: February 5, 2013
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Thomas J. Bucelot, Alan J. Drake, Robert A. Groves, Jason D. Hibbeler, Yong I. Kim, Liang-Teck Pang, William R. Reohr, Phillip J. Restle, Michael G. R. Thomson
  • Patent number: 9054682
    Abstract: A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit, a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid, at least one inductor, at least one tunable resistance switch, and a capacitor network. The tunable sector buffer is programmable to set latency and slew rate of the clock signal. The inductor, tunable resistance switch, and capacitor network are connected between the clock grid and a reference voltage. The at least one tunable resistance switch is programmable to dynamically switch the at least one inductor in or out of the clock distribution to effect at least one resonant mode of operation or a non-resonant mode of operation based on a frequency of the clock signal.
    Type: Grant
    Filed: February 5, 2013
    Date of Patent: June 9, 2015
    Assignee: International Business Machines Corporation
    Inventors: Thomas J. Bucelot, Alan J. Drake, Robert A. Groves, Jason D. Hibbeler, Yong I. Kim, Liang-Teck Pang, William R. Reohr, Phillip J. Restle, Michael G. R. Thomson
  • Patent number: 8887118
    Abstract: Recycling energy in a clock distribution network is provided. A method includes creating a resonant clocking circuit including a clock grid. The method further includes providing resonant structures distributed in the clock grid. The method further includes providing switches that control the resonant structures to switch between a non-resonant mode and a resonant mode. The method further includes determining a switch size that minimizes power consumption of the resonant clocking circuit by iteratively increasing sizes of the switches and, for each iterative increase in size, determining power consumed by the resonant clocking circuit.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: November 11, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jason D. Hibbeler, William R. Reohr, Phillip J. Restle
  • Patent number: 8863066
    Abstract: High performance clock distributions and similar wiring networks require improvements in reliability and performance. This is especially true when hierarchical wiring with different metal thicknesses is employed and when a smaller number of large, higher-power buffers are used to reduce timing variability. Routing of critical nets improves robustness, reliability, and resistance while minimizing track and power usage. The method further optimizes the use of multiple physical pins on buffers to achieve desired electrical criteria. This involves optimal selection of additional routing beyond what is needed to satisfy simple connectivity. The routing involves an iterative process to select and evaluate additional possible routes on multiple layers. Each iteration involves extraction and simulation or estimation, and additional routes are added until the desired electrical criteria are met.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: October 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Joseph N. Kozhaya, Phillip J. Restle, David Wen-Hao Shan
  • Patent number: 8850373
    Abstract: Recycling energy in a clock distribution network is provided. A method includes creating a resonant clocking circuit including a clock grid. The method further includes providing resonant structures distributed in the clock grid. The method further includes providing switches that control the resonant structures to switch between a non-resonant mode and a resonant mode. The method further includes determining a switch size that minimizes power consumption of the resonant clocking circuit by iteratively increasing sizes of the switches and, for each iterative increase in size, determining power consumed by the resonant clocking circuit.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: September 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jason D. Hibbeler, William R. Reohr, Phillip J. Restle
  • Publication number: 20140245250
    Abstract: Recycling energy in a clock distribution network is provided. A method includes creating a resonant clocking circuit including a clock grid. The method further includes providing resonant structures distributed in the clock grid. The method further includes providing switches that control the resonant structures to switch between a non-resonant mode and a resonant mode. The method further includes determining a switch size that minimizes power consumption of the resonant clocking circuit by iteratively increasing sizes of the switches and, for each iterative increase in size, determining power consumed by the resonant clocking circuit.
    Type: Application
    Filed: February 22, 2013
    Publication date: August 28, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jason D. HIBBELER, William R. REOHR, Phillip J. RESTLE
  • Publication number: 20140245244
    Abstract: Recycling energy in a clock distribution network is provided. A method includes creating a resonant clocking circuit including a clock grid. The method further includes providing resonant structures distributed in the clock grid. The method further includes providing switches that control the resonant structures to switch between a non-resonant mode and a resonant mode. The method further includes determining a switch size that minimizes power consumption of the resonant clocking circuit by iteratively increasing sizes of the switches and, for each iterative increase in size, determining power consumed by the resonant clocking circuit.
    Type: Application
    Filed: December 20, 2013
    Publication date: August 28, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jason D. HIBBELER, William R. REOHR, Phillip J. RESTLE