Patents by Inventor Phillip J. Restle

Phillip J. Restle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140245244
    Abstract: Recycling energy in a clock distribution network is provided. A method includes creating a resonant clocking circuit including a clock grid. The method further includes providing resonant structures distributed in the clock grid. The method further includes providing switches that control the resonant structures to switch between a non-resonant mode and a resonant mode. The method further includes determining a switch size that minimizes power consumption of the resonant clocking circuit by iteratively increasing sizes of the switches and, for each iterative increase in size, determining power consumed by the resonant clocking circuit.
    Type: Application
    Filed: December 20, 2013
    Publication date: August 28, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jason D. HIBBELER, William R. REOHR, Phillip J. RESTLE
  • Publication number: 20140240021
    Abstract: Recycling energy in a clock distribution network is provided. A method includes creating a resonant clocking circuit including a clock grid. The method further includes providing resonant structures distributed in the clock grid. The method further includes providing switches that control the resonant structures to switch between a non-resonant mode and a resonant mode. The method further includes determining a switch size that minimizes power consumption of the resonant clocking circuit by iteratively increasing sizes of the switches and, for each iterative increase in size, determining power consumed by the resonant clocking circuit.
    Type: Application
    Filed: December 20, 2013
    Publication date: August 28, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jason D. HIBBELER, William R. REOHR, Phillip J. RESTLE
  • Publication number: 20140223210
    Abstract: A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit and a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid. The tunable sector buffer is configured to set latency and slew rate of the clock signal based on an identified resonant or non-resonant mode.
    Type: Application
    Filed: February 5, 2013
    Publication date: August 7, 2014
    Applicant: International Business Machines Corporation
    Inventors: Thomas J. Bucelot, Alan J. Drake, Robert A. Groves, Jason D. Hibbeler, Yong I. Kim, Liang-Teck Pang, William R. Reohr, Phillip J. Restle, Michael G.R. Thomson
  • Publication number: 20140218087
    Abstract: A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit, a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid, at least one inductor, at least one tunable resistance switch, and a capacitor network. The tunable sector buffer is programmable to set latency and slew rate of the clock signal. The inductor, tunable resistance switch, and capacitor network are connected between the clock grid and a reference voltage. The at least one tunable resistance switch is programmable to dynamically switch the at least one inductor in or out of the clock distribution to effect at least one resonant mode of operation or a non-resonant mode of operation based on a frequency of the clock signal.
    Type: Application
    Filed: February 5, 2013
    Publication date: August 7, 2014
    Applicant: International Business Machines Corporation
    Inventors: Thomas J. Bucelot, Alan J. Drake, Robert A. Groves, Jason D. Hibbeler, Yong I. Kim, Liang-Teck Pang, William R. Reohr, Phillip J. Restle, Michael G.R. Thomson
  • Patent number: 8704576
    Abstract: A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit, at least one inductor, at least one tunable resistance switch, and a capacitor network. The inductor, tunable resistance switch, and capacitor network are connected between the clock grid and a reference voltage. The at least one tunable resistance switch is programmable to dynamically switch the at least one inductor in or out of the clock distribution to effect at least one resonant mode of operation or a non-resonant mode of operation based on a frequency of the clock signal.
    Type: Grant
    Filed: February 5, 2013
    Date of Patent: April 22, 2014
    Assignee: International Business Machines Corporation
    Inventors: Thomas J. Bucelot, Alan J. Drake, Robert A. Groves, Jason D. Hibbeler, Yong I. Kim, Liang-Teck Pang, William R. Reohr, Phillip J. Restle, Michael G. R. Thomson
  • Patent number: 8525569
    Abstract: There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. On each of the two or more strata, the clock distribution network includes a clock grid having a plurality of sectors for providing the global clock signals to various chip locations, a multiple-level buffered clock tree for driving the clock grid and including at least a root and a plurality of clock buffers, and one or more multiplexers for providing the global clock signals to at least a portion of the buffered clock tree. Inputs of at least some of the plurality of clock buffers on each of the two or more strata are shorted together using chip-to-chip interconnects to reduce skewing of the global clock signals with respect to the various chip locations.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: September 3, 2013
    Assignee: International Business Machines Corporation
    Inventors: Thomas J. Bucelot, Liang-Teck Pang, Phillip J. Restle
  • Patent number: 8516426
    Abstract: A method is provided for managing power distribution on a three-dimensional chip stack having two or more strata, a plurality of vertical power delivery structures, and multiple stack components. At least two stack components are on different strata. Operating modes are stored that respectively have different power dissipations. A respective effective power budget is determined for each of the at least two stack components based on respective ones of the operating modes targeted therefor, and power characteristics and thermal characteristics of at least some of the stack components inclusive or exclusive of the at least two stack components. The respective ones of the plurality of operating modes targeted for the at least two stack components are selectively accepted or re-allocated based on the respective effective power budget for each of the at least two stack components, power constraints, and thermal constraints. The power constraints include vertical structure electrical constraints.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: August 20, 2013
  • Publication number: 20130049827
    Abstract: There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. On each of the two or more strata, the clock distribution network includes a clock grid having a plurality of sectors for providing the global clock signals to various chip locations, a multiple-level buffered clock tree for driving the clock grid and including at least a root and a plurality of clock buffers, and one or more multiplexers for providing the global clock signals to at least a portion of the buffered clock tree. Inputs of at least some of the plurality of clock buffers on each of the two or more strata are shorted together using chip-to-chip interconnects to reduce skewing of the global clock signals with respect to the various chip locations.
    Type: Application
    Filed: August 25, 2011
    Publication date: February 28, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: THOMAS J. BUCELOT, LIANG-TECK PANG, PHILLIP J. RESTLE
  • Publication number: 20130055185
    Abstract: A method is provided for managing power distribution on a 3D chip stack having two or more strata, a plurality of vertical power delivery structures, and multiple stack components. At least two stack components are on different strata. Operating modes are stored that respectively have different power dissipations. A respective effective power budget is determined for each of the at least two stack components based on respective ones of the operating modes targeted therefor, and power characteristics and thermal characteristics of at least some of the stack components inclusive or exclusive of the at least two stack components. The respective ones of the plurality of operating modes targeted for the at least two stack components are selectively accepted or re-allocated based on the respective effective power budget for each of the at least two stack components, power constraints, and thermal constraints. The power constraints include vertical structure electrical constraints.
    Type: Application
    Filed: August 25, 2011
    Publication date: February 28, 2013
  • Publication number: 20120124669
    Abstract: A mechanism is provided for protecting a layer of functional units from side-channel attacks. A determination is made as to whether one or more subsets of functional units in a set of functional units in the layer of functional units is performing operations of a critical nature. Responsive to a determination that there is one or more subsets of functional units that are performing the operations of the critical nature, at least one concealing pattern is generated in a concealing layer in order to conceal the operations of the critical nature being performed by each of the subset of functional units. The concealing layer is electrically and physically coupled to the layer of functional units.
    Type: Application
    Filed: November 12, 2010
    Publication date: May 17, 2012
  • Patent number: 7961559
    Abstract: A circuit and method for measuring duty cycle uncertainty in an on-chip global clock. A global clock is provided to a delay line at a local clock buffer. Delay line taps (inverter outputs) are inputs to a register that is clocked by the local clock buffer. The register captures clock edges, which are filtered to identify a single location for each edge. Imbalance in space between the edges indicated imbalance in duty cycle. Up/down signals are generated from any imbalance and passed to a phase locked loop to adjust the balance.
    Type: Grant
    Filed: August 12, 2009
    Date of Patent: June 14, 2011
    Assignee: International Business Machines Corporation
    Inventors: Robert C. Dixon, Robert L. Franch, Phillip J. Restle
  • Publication number: 20090295449
    Abstract: A circuit and method for measuring duty cycle uncertainty in an on-chip global clock. A global clock is provided to a delay line at a local clock buffer. Delay line taps (inverter outputs) are inputs to a register that is clocked by the local clock buffer. The register captures clock edges, which are filtered to identify a single location for each edge. Imbalance in space between the edges indicated imbalance in duty cycle. Up/down signals are generated from any imbalance and passed to a phase locked loop to adjust the balance.
    Type: Application
    Filed: August 12, 2009
    Publication date: December 3, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert C. Dixon, Robert L. Franch, Phillip J. Restle
  • Patent number: 7571410
    Abstract: An integrated circuit (IC), IC assembly and circuit for distributing a clock signal in an integrated circuit includes a capacitive clock distribution circuit having at least one conductor therein. At least one inductor is formed in a metal layer of the integrated circuit and is coupled to the clock distribution circuit. The inductor, generally in the form of a number of spiral inductors distributed throughout the integrated circuit, provides an inductance value selected to resonate with the capacitive clock distribution circuit at resonance, power dissipation is reduced while skew and jitter performance can be improved.
    Type: Grant
    Filed: April 26, 2007
    Date of Patent: August 4, 2009
    Assignee: International Business Machines Corporation
    Inventor: Phillip J. Restle
  • Patent number: 7456671
    Abstract: A hierarchical and modular clock programmable delay circuit structure is described that can achieve almost unlimited fine resolution and unlimited delay range. The same circuit may also be applied to critical circuits that require fine adjustment in timing applications. The modular design allows the circuit and its layout to be synthesized by software to achieve desired delay resolution and range. Constant capacitive load of internal node enhances the linearity of achieved delay by digital controls.
    Type: Grant
    Filed: January 11, 2007
    Date of Patent: November 25, 2008
    Assignee: International Business Machines Corporation
    Inventors: Charlie C. Hwang, Phillip J. Restle, Leon J. Sigal
  • Publication number: 20080198699
    Abstract: A circuit for measuring timing uncertainty in a clocked digital path and in particular, the number of logic stages completed in any clock cycle. A local clock buffer receives a global clock and provides a complementary pair of local clocks. A first local (launch) clock is an input to a delay line, e.g., 3 clock cycles worth of series connected inverters. Delay line taps (inverter outputs) are inputs to a register that is clocked by the complementary clock pair to capture progression of the launch clock through the delay line and identify any variation (e.g., from jitter, VDD noise) in that progression. Global clock skew and across chip gate length variation can be measured by cross coupling launch clocks from a pair of such clock buffers and selectively passing the local and remote launch clocks to the respective delay lines.
    Type: Application
    Filed: March 10, 2008
    Publication date: August 21, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert L. Franch, William V. Huott, Norman K. James, Phillip J. Restle, Timothy M. Skergan
  • Publication number: 20080198700
    Abstract: A circuit for measuring timing uncertainty in a clocked digital path and in particular, the number of logic stages completed in any clock cycle. A local clock buffer receives a global clock and provides a complementary pair of local clocks. A first local (launch) clock is an input to a delay line, e.g., 3 clock cycles worth of series connected inverters. Delay line taps (inverter outputs) are inputs to a register that is clocked by the complementary clock pair to capture progression of the launch clock through the delay line and identify any variation (e.g., from jitter, VDD noise) in that progression. Global clock skew and across chip gate length variation can be measured by cross coupling launch clocks from a pair of such clock buffers and selectively passing the local and remote launch clocks to the respective delay lines.
    Type: Application
    Filed: March 10, 2008
    Publication date: August 21, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert L. Franch, William V. Huott, Norman K. James, Phillip J. Restle, Timothy M. Skergan
  • Publication number: 20080169857
    Abstract: A hierarchical and modular clock programmable delay circuit structure is described that can achieve almost unlimited fine resolution and unlimited delay range. The same circuit may also be applied to critical circuits that require fine adjustment in timing applications. The modular design allows the circuit and its layout to be synthesized by software to achieve desired delay resolution and range. Constant capacitive load of internal node enhances the linearity of achieved delay by digital controls.
    Type: Application
    Filed: January 11, 2007
    Publication date: July 17, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charlie C Hwang, Phillip J. Restle, Leon J. Sigal
  • Patent number: 7400555
    Abstract: A circuit for measuring timing uncertainty in a clocked digital path and in particular, the number of logic stages completed in any clock cycle. A local clock buffer receives a global clock and provides a complementary pair of local clocks. A first local (launch) clock is an input to a delay line, e.g., 3 clock cycles worth of series connected inverters. Delay line taps (inverter outputs) are inputs to a register that is clocked by the complementary clock pair to capture progression of the launch clock through the delay line and identify any variation (e.g., from jitter, VDD noise) in that progression. Global clock skew and across chip gate length variation can be measured by cross coupling launch clocks from a pair of such clock buffers and selectively passing the local and remote launch clocks to the respective delay lines.
    Type: Grant
    Filed: November 13, 2003
    Date of Patent: July 15, 2008
    Assignee: International Business Machines Corporation
    Inventors: Robert L. Franch, William V. Huott, Norman K. James, Phillip J. Restle, Timothy M. Skergan
  • Patent number: 7237217
    Abstract: An integrated circuit (IC), IC assembly and circuit for distributing a clock signal in an integrated circuit includes a capacitive clock distribution circuit having at least one conductor therein. At least one inductor is formed in a metal layer of the integrated circuit and is coupled to the clock distribution circuit. The inductor, generally in the form of a number of spiral inductors distributed throughout the integrated circuit, provides an inductance value selected to resonate with the capacitive clock distribution circuit at resonance, power dissipation is reduced while skew and jitter performance can be improved.
    Type: Grant
    Filed: November 24, 2003
    Date of Patent: June 26, 2007
    Assignee: International Business Machines Corporation
    Inventor: Phillip J. Restle
  • Patent number: 6933754
    Abstract: A supply noise compensation circuit. The supply noise compensation circuit senses the onset of dI/dt noise events on a supply line and selectively gates off/forces on a chip clock to chip circuits.
    Type: Grant
    Filed: November 13, 2003
    Date of Patent: August 23, 2005
    Assignee: International Business Machines Corp.
    Inventor: Phillip J. Restle