Abstract: A circuit comprises an array of memory cells (10). A plurality of sensing circuits (20), are coupled to the output (14) of respective memory cells (10), for comparing the output signal of the respective one of the memory cells (10) with a reference signal to form a data signal from the output signal from the respective one of the memory cells (10). A reference generator circuit (24, 26) forms the reference signal from a sum wherein each respective one of the memory cells (10) of the addressed group contributes a contribution that is a function of the output signal of the respective one of the memory cells (10). The contributions are equalized for output signal values at more than a saturating distance above the reference signal, and the contributions are equalized for output signal values at more than the saturating distance below the reference signal.

Abstract: Recordable DVD+R and DVD+R/W optical discs with two (or more) information layers are developed to double the data storage capacity and video recording time. A method and device are proposed to make dual layer DVD disc recordings compliant with the dual layer DVD-ROM standard Recording the data in a DVD-ROM compliant way on the dual layer DVD+R or DVD+R/W disc is obtained by shifting the middle zone area towards the inner radius of a disc in such a way that the data zones of both layers are filled up with data.

Abstract: The present invention relates to a recording apparatus, record carrier and method of recording data on at least two layers of a recording medium by using a radiation power, wherein individual recording speeds are determined for respective ones of the at least two layers at different values of the radiation power. A recording speed to be used for recording on an individual one of the at least two recording layers is selected based on a maximum radiation power specified for the recording operation, and the speed of the recording operation is controlled individually for each of the at least two layers based on the selected recording speed. The determination of the individual recording speeds at different radiation power values may be written or embossed on the record carrier. Furthermore, a recording sequence used for recording on the recording layers can be set based on the sensitivities and thus recording speeds. Thereby, total recording time can be minimized for multi-layer recording media.

Abstract: The present invention relates to a recording apparatus, record carrier and method of recording data on at least two layers of a recording medium by using a radiation power, wherein individual recording speeds are determined for respective ones of the at least two layers at different values of the radiation power. A recording speed to be used for recording on an individual one of the at least two recording layers is selected based on a maximum radiation power specified for the recording operation, and the speed of the recording operation is controlled individually for each of the at least two layers based on the selected recording speed. The determination of the individual recording speeds at different radiation power values may be written or embossed on the record carrier. Furthermore, a recording sequence used for recording on the recording layers can be set based on the sensitivities and thus recording speeds. Thereby, total recording time can be minimized for multi-layer recording media.

Abstract: An amplifier/buffer composed from circuit elements of a single threshold and single conductivity type, comprising an input stage for receiving one or more inputs for buffering/amplification and providing an intermediate to control output of the amplifier/buffer. The intermediate signal is provided to a boosting circuit configured to boosts said signal when said signal has exceeded a predetermined value. The amplifier/buffer further has an output stage for receiving at least said signal and providing an amplified/buffered output.

Abstract: A multi-layer record carrier is for recording information by writing marks in a track. The record carrier has a first recording layer (40) and a second recording layer (41), and each recording layer has a pregroove (14) indicating the position of the track according to an opposite track path. The pregroove exhibits a modulated wobble for representing control information. A lead-in part of the pregroove has first control information for the first recording layer, and the lead-out part on the second recording layer has second control information including recording parameters for the second recording layer. The device the device has a head (22) for providing the beam and wobble detection means (32) for retrieving control information from each layer.

Abstract: Recordable DVD+R and DVD+R/W optical discs with two (or more) information layers are developed to double the data storage capacity and video recording time. A method and device are proposed to make dual layer DVD disc recordings compliant with the dual layer DVD-ROM standard Recording the data in a DVD-ROM compliant way on the dual layer DVD+R or DVD+R/W disc is obtained by shifting the middle zone area towards the inner radius of a disc in such a way that the data zones of both layers are filled up with data.

Abstract: In an example embodiment, an electronic circuit comprises a memory matrix with rows and columns of memory cells. First row conductors are provided for each of the rows. Second row conductors correspond to pairs of rows, each successive row forming a respective pair with a preceding one of the rows, so that each pair overlaps with one row of the next pair. Column conductors are provided for each of the columns. Each of the memory cells comprises an access transistor, a node and a first and a second resistive memory element. The access transistor has a control electrode coupled to the first row conductor of the row of the memory cell, a main current channel coupled between the column conductor for the column of the memory cell and the node. The first and second the resistive memory element are coupled between the node and the second row conductors for the pairs of rows to which the memory cell belongs.

Abstract: A logic assembly (400) is composed from circuit elements of a single threshold and single conductivity type and comprises a logic circuitry (410) having at least a set of switches each having a main current path and a control terminal. The main current path forms a series arrangement having first and second conducting terminals coupled to power supply lines. The main current paths being coupled to a common node that forms an output of logic assembly (400). The control terminals of said switches being coupled to clock circuitry for providing mutually non-overlapping clock signals to said control terminal. The logic assembly further comprises an output boosting circuit (420) for boosting the output of said logic assembly (400) including a capacitive means (421) for enabling supply of additional charge to the output of said logic assembly (400).

Abstract: A memory matrix (10) comprises rows and columns of cells, each cell comprising a resistance hysteresis element (24) and a threshold element (22) coupled in series between a row terminal and a column terminal of the cell (20). The resistance hysteresis element (24) has a mutually larger and smaller hysteresis thresholds of mutually opposite polarity respectively. Voltage differences are applied between the column terminals and the row terminals of cells (20) in a selected row, so as to perform read actions. These voltage differences have a read polarity so that the voltage across the cell (20) is in a direction corresponding to the larger hysteresis threshold. Voltage differences are applied between the column terminals and the row terminals of cells (20) in a selected row, so as to perform erase actions, all cells (20) of a selected row being erased collectively in the erase action. The voltage differences for erase actions have the read polarity.

Abstract: The invention discloses a method and a device for recording information on a multi layer optical disc using a multi session format. The use of multi sessions allows for an efficient use of the storage capacity of the disc, and for a fast finalization time.

Abstract: The present invention relates to a detector configuration, pickup device and driving device for multi-layer record carriers, wherein main beam detector means and two pairs of side-beam detector means disposed on opposite sides of the main beam detector means are provided for suppressing crosstalk effects. As an example, the two three-spot systems obtained can be used for focus error signals and tracking error signals, respectively, wherein satellite spots can be controlled to have a desired fringe pattern either in-phase or anti-phase with that of the main beam. Besides the reduction of focusing and tracking errors, the above measure allows to reduce spacer layer thickness.

Abstract: Recordable DVD+R and DVD+R/W optical discs with two (or more) information layers are developed to double the data storage capacity and video recording time. A method and device are proposed to make dual layer DVD disc recordings compliant with the dual layer DVD-ROM standard Recording the data in a DVD-ROM compliant way on the dual layer DVD+R or DVD+R/W disc is obtained by shifting the middle zone area towards the inner radius of a disc in such a way that the data zones of both layers are filled up with data.

Abstract: A control circuit (1, 11) for a memory matrix is used that defines a write process that uses circuit state transitions between at least two idle circuit states, an all column update circuit state and a column selective update state. In the second. During access the control circuit switches back and forth to the column selective update state (W) from the first idle state (II) during execution of a column selective update command and back and forth to the all-column update state (E) from the second idle state (12) during execution of an all column update command. The control circuit (1, 11) is retained in the first and second idle state (II, 12), without switching to the second and first idle state (12, II) between execution of successive column selective update commands and all column update commands respectively.

Abstract: The electric device (100) according to the invention comprises a layer (107) of a memory material which has an electrical resistivity switchable between a first value and a second value. The memory material may be a phase change material. The electric device (100) further comprises a set of nanowires (NW) electrically connecting a first terminal (172) of the electric device and the layer (107) of memory material thereby enabling conduction of an electric current from the first terminal via the nanowires (NW) and the layer (107) of memory material to a second terminal (272) of the electric device. Each nanowire (NW) electrically contacts the layer (107) of memory material in a respective contact area. All contact areas are substantially identical. The method according to the invention is suited to manufacture the electric device (100) according to the invention.

Abstract: A memory matrix (10) comprises rows and columns of cells, each cell comprising a resistance hysteresis element (24) and a threshold element (22) coupled in series between a row terminal and a column terminal of the cell (20). The resistance hysteresis element (24) has a mutually larger and smaller hysteresis thresholds of mutually opposite polarity respectively. Voltage differences are applied between the column terminals and the row terminals of cells (20) in a selected row, so as to perform read actions. These voltage differences have a read polarity so that the voltage across the cell (20) is in a direction corresponding to the larger hysteresis threshold. Voltage differences are applied between the column terminals and the row terminals of cells (20) in a selected row, so as to perform erase actions, all cells (20) of a selected row being erased collectively in the erase action. The voltage differences for erase actions have the read polarity.

Abstract: A control circuit (1, 11) for a memory matrix is used that defines a write process that uses circuit state transitions between at least two idle circuit states, an all column update circuit state and a column selective update state. In the second. During access the control circuit switches back and forth to the column selective update state (W) from the first idle state (II) during execution of a column selective update command and back and forth to the all-column update state (E) from the second idle state (12) during execution of an all column update command. The control circuit (1, 11) is retained in the first and second idle state (II, 12), without switching to the second and first idle state (12, II) between execution of successive column selective update commands and all column update commands respectively.

Abstract: This invention relates to a method for recording information on a multi layer record carrier. The information is recorded on the record carrier according to special filling patterns, such that the record carrier is compatible with the DVD-ROM standard while the time required for closing a session and/or finalizing the disc is reduced. The information is substantially evenly distributed over the layers in blocks of a predefined amount of storage space. The size of these blocks may be flexible and set by the method or read from the record carrier.

Abstract: An electronic circuit comprises a memory matrix (60) with rows and columns of memory cells (16). First row conductors (10, 12) are provided for each of the rows. Second row conductors (12) are provided for successively overlapping pairs of adjacent rows. Column conductors (14) are provided for each of the columns. Each of the memory cells (16) comprises an access transistor (160), a node (166) and a first and second resistive memory element (162, 164). The access transistor (160) is preferably a vertical transistor having a control electrode coupled to the first row conductor (10) of the row of the memory cell (16), a main current channel coupled between the column conductor (14) for the column of the memory cell (160) and the node (166). The first and second resistive memory element (162, 164) are coupled between the node (166) and the second row conductors (12) for the pairs of rows to which the memory cell belongs.

Abstract: A memory (10) is organized as a matrix rows and columns of memory cell circuits (100) and comprises bit line conductors (12) coupled to rows of the memory cells (100). A sensing circuit (14) is coupled to the bit line conductors (12). The sensing circuit (14) is arranged to form respective data signals, each by comparing a respective signal from a plurality of the bit line conductors (12) with a reference level that is common for the bit line conductors (12). A reference level selection circuit (16) with inputs coupled to the plurality of bit line conductors (12) is arranged to control the reference level. The reference level selection circuit (16) selects the reference level dependent on respective analog signal levels on the plurality of the bit line conductors (12), so that analog signal levels from at least respective ones of the plurality of bit line conductors (12) lie on respective sides of the reference level.