Patents by Inventor Pierre Jeuch

Pierre Jeuch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4541892
    Abstract: An improvement to the process for positioning an interconnection line on an electrical contact hole of an integrated circuit, according to which between a photosensitive coating and an insulating coating is interposed an intermediate anti-reflecting coating made e.g. from SiO.sub.2 or amorphous silicon. The SiO.sub.2 intermediate coating, etched after irradiation of the photosensitive material coating, is used as a mask for reactive ionic etching of the insulating coating. Thus, the image of the photosensitive material coating is transferred to the thick insulating material coating. This process is useful especially in the production of integrated circuits.
    Type: Grant
    Filed: August 10, 1984
    Date of Patent: September 17, 1985
    Assignee: Commissariat a l'Energie Atomique
    Inventor: Pierre Jeuch
  • Patent number: 4518629
    Abstract: Process for positioning an electrical contact hole between a first and a second interconnection line of an integrated circuit. The first interconnection line is produced by depositing an insulating coating on the complete integrated circuit, depositing a first material coating on said insulating coating, etching the first material coating, defining the dimensions of the electrical contact hole by masking with resin, etching the insulating coating, eliminating the mask and the remaining first material coating.The second interconnection line is produced by depositing a conductive coating on the complete integrated circuit, on which is deposited a second material coating, which is etched, so as to only leave material at the locations of the electrical contact hole, followed by the deposition of a resin coating, etching the area of the conductive coating where there is neither resin nor the residual second material coating and eliminating the latter and the resin coating.
    Type: Grant
    Filed: December 8, 1983
    Date of Patent: May 21, 1985
    Assignee: Commissariat a l'Energie Atomique
    Inventor: Pierre Jeuch
  • Patent number: 4505030
    Abstract: Process for the positioning of an interconnection line on an electrical contact hole of an integrated circuit, wherein, when the electrical contact hole has been produced, the following stages are performed:deposition of a conductive layer in which the interconnection line is to be formed on the complete integrated circuit;deposition on the conductive layer of an insulating layer blanking the relief thereof and having a planar surface,etching the insulating layer, so that insulating material is only left at the location of the electrical contact hole,deposition of a resin layer on the integrated circuit, so as to mask the interconnection line to be produced,etching of that part of the conductive layer which is free from resin and the residual insulating layer, andelimination of the remaining insulating layer and the resin layer.The positioning process is particularly used in processes for producing MOS integrated circuits.
    Type: Grant
    Filed: April 12, 1983
    Date of Patent: March 19, 1985
    Assignee: Commissariat a l'Energie Atomique
    Inventor: Pierre Jeuch
  • Patent number: 4455193
    Abstract: Process for producing the field oxide of an integrated circuit, wherein it comprises the following successive stages:(a) producing a resin mask on a first region of a doped semiconductor substrate, in which will be formed the active component of the integrated circuit,(b) production of a first etching over a height h of a second region of the doped semiconductor substrate, in which it is wished to produce the field oxide,(c) implantation of ions in the second region of the remaining substrate, giving a doping of the same type as that of the substrate,(d) deposition of an insulating layer on the complete substrate,(e) deposition of a resin layer on the insulating layer,(f) production of a second simultaneous etching of the resin layer and the insulating layer, until the complete elimination of that region of the oxide layer positioned above the first region of the substrate in which will be produced the active component of the integrated circuit.
    Type: Grant
    Filed: June 29, 1983
    Date of Patent: June 19, 1984
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Pierre Jeuch, Pierre Parrens