Abstract: A method for determining translation portion of misalignment error in a stepper. In one embodiment, the method comprises a series of steps in a stepper, starting with the step of receiving a wafer in the stepper. In another step a first pattern, including an error-free fine alignment target, is created on the wafer. Next, the wafer is realigned in the stepper using the error-free fine alignment target. Then a second pattern is created on the wafer overlaying said first pattern. In another step, the translational error between the first pattern and the second pattern is measured.

Abstract: Semiconductor wafer processing methods are described. In one implementation, a semiconductor wafer is provided with a layer of photoresist thereover. A matrix is defined within the photoresist and comprises a plurality of exposed grating patterns which are formed through successive exposure passes of a mask which defines the grating pattern. The wafer is exposed to conditions which are effective to remove at least some of the photoresist and to clear substantially all of the photoresist over a wafer portion underlying at least one of the exposed grating patterns. The wafer is inspected and at least one processing parameter associated with photoresist which was removed during processing can be ascertained. In a preferred aspect, the processing parameter comprises an illumination exposure dosage. In a preferred implementation, two exposure passes with the mask are made with a second of the passes being shifted by a predetermined amount relative to the grating pattern defined by the first pass.

Abstract: Discloses is an apparatus and method for cleaning the edges of semiconductor wafers by using a particle withdrawing means having pre-formed, low-tack adhesive material that removes the particles from the edges of the wafers and retains the particles thus removed.

Abstract: The effectiveness of various types of optical proximity correction schemes for avoiding line shortening are easily evaluated by imprinting a test pattern on a semiconductor wafer. The pattern includes an easily measurable standard measurement element not susceptible to line shortening and a test element having a series of parallel lines with narrow widths comparable to the widths of the circuit features that are susceptible to line shortening. The test element also includes the same optical proximity correction scheme whose effectiveness is to be measured. The entire test pattern is photolithographed onto the wafer and the lengths of measurement element and the test element are measured and compared to determine the effectiveness of the correction. Several test patterns, each with a different form of optical proximity correction, can be lithographed onto a single wafer for a comparative review of the different correction schemes both in focus and out of focus both positively and negatively.

Abstract: A method for verifying the accuracy of an average topography height function of a photostepper is provided, which includes the steps of placing a wafer on the photostepper for subjecting at least one layout disposed thereon to the average topography height function of the photostepper, wherein the layout has a known average topography height; operating the average topography height function of the photostepper to obtain a measured average topography height; and comparing the measured topography height to the known average topography height. A method for compensating for an inaccuracy of the average topography height function of the photostepper which includes the same steps for verifying the function, whereby an error results; and adds the step of compensating subsequent measurements of the average topography height function by a correcting factor equal to the magnitude of the error.

Abstract: Line shortening and other defects in integrated circuits are measured by imprinting accuracy determinative patterns in the scribe lines or die margins of the mask field. The patterns are ideally formed in the general nature of the usual box in a box configuration with one of the boxes being specially configured to include a series of lines and spaces having narrow widths comparable to the width of the lines to be formed in the integrated circuit. The use of the narrow lines provides the box in a box configuration with the same line shortening that the circuit feature will itself experience. Small spaces between the lines permit the standard measuring equipment to locate at the ends of the lines.

Abstract: A method of forming a focus/exposure matrix on a wafer is provided, wherein the wafer is used to calibrate the photostepper's focus and exposure time settings. The focus/exposure matrix comprising a series of patterns disposed on the wafer. The patterns being arranged in rows and columns. The patterns in a row being characterized by having been formed with substantially the same exposure time and an effective focus that increments between successive row patterns by an amount substantially corresponding to half the focus resolution of the photostepper. The patterns in a column being characterized by having been formed with substantially the same effective focus and an exposure time that increments between successive column patterns by a finite amount.

Abstract: A focus/exposure matrix comprises a series of patterns disposed on a wafer. The patterns are arranged in rows and columns. The patterns in a row are characterized by having been formed with substantially the same exposure time and an effective focus that increments between successive row patterns by an amount substantially corresponding to half the focus resolution of the photostepper. The patterns in a column are characterized by having been formed with substantially the same effective focus and an exposure time that increments between successive column patterns by a finite amount.

Abstract: A method for measuring alignment accuracy in a step and repeat system which includes projecting an array of rows and columns of grating features onto a wafer coated with a resist using a first stepping distance and using an increased exposure dosage from row to row of said array; projecting the same array over the first but using a different stepping distance along the rows and also a sufficient offset in the starting positions of the first and second exposures to form a phase difference between the two projection exposures which will result in a complementary alignment of the two exposures at least one column in the array.

Abstract: A method is described for reducing light scatter in lithographically producing a resist feature wherein the dosage of light beyond the immediate periphery of the desired feature is subjected to a lower dosage of light than is required to properly define the edges of the resist feature. In addition, a mask is described which is partially opaque in those areas remote from the area delineating the desired feature.

Abstract: A particle removal wafer including ridges defining recessed areas and sticky material placed in these recessed areas can be run through wafer processing equipment. The particle removal wafer can remove particles that would otherwise adhere to the backs of wafers run through this equipment. Particles adhering to the backs of wafers are a problem in the photolithographic steps. These particles cause the focus of the photolithographic system to be off and thus can cause fatal errors. By removing the particles which could adhere to the backs of wafers from the wafer fabrication equipment, the accuracy of the photolithographic process can be improved.

Abstract: Ultra-small equal-width lines and spaces are generated on an integrated circuit wafer using multiple exposures and phase-shifting at the wafer level. In particular, an integrated circuit wafer is coated with a layer of photoresist and then masked using a mask defining a pattern of multiple feature lines arranged at a regular line pitch. The layer of photoresist is then underexposed so as to partially bleach portions of the layer of photoresist in accordance with the pattern. Next, the mask and the integrated circuit wafer are positionally translated relative to one another by a predetermined fraction of the line pitch, and the layer of photoresist is then again underexposed. Developing the photoresist layer creates a stepped profile. The layer of photoresist is then blanket exposed, the stepped profile causing exposure in the vicinity of steps to be retarded. The layer of photoresist is then developed, producing thin lines of photoresist separated by substantially equal spaces of no photoresist.

Abstract: Method and apparatus for detecting the presence of selected types of defects, such as chemical stains from a liquid photoresist material or a liquid dielectric material, on a non-visible chosen surface of a semiconductor water that has undergone at least one processing step. In one embodiment, a support substrate for, the wafer is provided that has a highly reflecting surface adjacent to the chosen surface. The reflecting surface and the chosen surface are moved apart, and the chosen surface is illuminated with light to form an optical image of the chosen surface. The optical image of the chosen surface is reflected in the reflecting surface, and the reflected optical image is examined for the presence of selected types of defects. In another embodiment, a portion of this reflecting surface is initially contiguous to the chosen surface.

Abstract: Disclosed herein is an apparatus and method for cleaning the edges of semiconductor wafers by using a particle removing means having an electrostatically charged material. The particles are collected and disposed of so that they do not come in contact again with the clean semiconductor wafers.