Abstract: The input interface for a transmit/receive radio station includes an input for receiving a signal either with a variable voltage over a pre-determined voltage range, or an open collector signal having a voltage (0V) corresponding to the low logic state; a first output for the variable voltage signal, and a second open collector output. The first and second outputs are connected to the same input and the input is connected to a reference potential through a first voltage divider bridge, the middle point of which is connected to the positive terminal of an open loop comparator, the output of which is connected to the second output.

Abstract: The input interface for a transmit/receive radio station includes an input for receiving a signal either with a variable voltage over a pre-determined voltage range, or an open collector signal having a voltage (0V) corresponding to the low logic state; a first output for the variable voltage signal, and a second open collector output. The first and second outputs are connected to the same input and the input is connected to a reference potential through a first voltage divider bridge, the middle point of which is connected to the positive terminal of an open loop comparator, the output of which is connected to the second output.

Abstract: A circuit for switching clocks includes a first input intended to receive a first clock signal at a frequency alternately equal to a first value or a second value, a second input intended to receive a second clock signal, synchronous with the first clock signal, at a third frequency and an output intended to deliver a third clock signal at a frequency alternately equal to the first value or the third value.

Abstract: A circuit for switching clocks includes a first input intended to receive a first clock signal at a frequency alternately equal to a first value or a second value, a second input intended to receive a second clock signal, synchronous with the first clock signal, at a third frequency and an output intended to deliver a third clock signal at a frequency alternately equal to the first value or the third value.

Abstract: A synchronizing system for a private digital exchange (1) comprising a logic control unit (4) and specialized interfaces (9, 8) whereby the exchange is connected firstly to a plurality of subscriber terminals (2) via SO accesses, and secondly to a telecommunications network (3) via TO base accesses. The exchange includes a time base (6) which associates a fixed frequency local oscillator (7) with a phase locked loop (32). The system includes clock switching means suitable for imposing the first clock signals to come from the network (3) via an active one of the TO base accesses and the associated interface (8) on the phase locked loop (32) of the time base (6) as soon as said first clock signals come close in phase to the substitute clock signals provided by the time base (6) in the absence of said first signals from the network.