Patents by Inventor Pin-Chieh WU

Pin-Chieh WU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200403077
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.
    Type: Application
    Filed: September 4, 2020
    Publication date: December 24, 2020
    Inventors: Chun-Chieh Chiu, Pin-Hong Chen, Yi-Wei Chen, Tsun-Min Cheng, Chih-Chien Liu, Tzu-Chieh Chen, Chih-Chieh Tsai, Kai-Jiun Chang, Yi-An Huang, Chia-Chen Wu, Tzu-Hao Liu
  • Publication number: 20200350317
    Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).
    Type: Application
    Filed: July 16, 2020
    Publication date: November 5, 2020
    Inventors: Pin-Hong Chen, Tsun-Min Cheng, Chih-Chieh Tsai, Tzu-Chieh Chen, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Li-Wei Feng, Ying-Chiao Wang, Chung-Yen Feng
  • Patent number: 10804365
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: October 13, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chun-Chieh Chiu, Pin-Hong Chen, Yi-Wei Chen, Tsun-Min Cheng, Chih-Chien Liu, Tzu-Chieh Chen, Chih-Chieh Tsai, Kai-Jiun Chang, Yi-An Huang, Chia-Chen Wu, Tzu-Hao Liu
  • Patent number: 10802301
    Abstract: The optical response of a metasurface is controlled by actuating it via an electrical or magnetic field, temperature control, optical pumping or electromechanical actuation. The metasurface will therefore control the polarization of the incident light. The metasurface comprises an array of patch antennas. The patch antennas are in the form of asymmetrical elements, including rotated rods, cross-shapes, V-shapes, and L-shapes.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: October 13, 2020
    Assignee: CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventors: Pin Chieh Wu, Ruzan Sokhoyan, Ghazaleh Kafaie Shirmanesh, Harry A. Atwater
  • Publication number: 20200280174
    Abstract: A light modulation element according to example embodiments includes a substrate; a first lower DBR layer on the substrate including a first material layer alternately stacked with a second material layer having a different refractive index from the first material layer; a second lower DBR layer on the first lower DBR layer with a surface area less than the first lower DBR layer and including a third material layer alternately stacked with a fourth material layer having a different refractive index from the third material layer; an active layer on the second lower DBR layer, including a semiconductor material having a multi-quantum well structure and having a refractive index that varies according to an applied voltage; and an upper DBR layer on the active layer including a fifth material layer alternately stacked with a sixth material layer having a different refractive index from the fifth material layer.
    Type: Application
    Filed: February 28, 2020
    Publication date: September 3, 2020
    Applicants: SAMSUNG ELECTRONICS CO., LTD., CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventors: Duhyun LEE, Muhammad ALAM, Ghazaleh KAFAIE SHIRMANESH, Harry ATWATER, Pin Chieh WU, Ragip PALA
  • Patent number: 10756090
    Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: August 25, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Pin-Hong Chen, Tsun-Min Cheng, Chih-Chieh Tsai, Tzu-Chieh Chen, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Li-Wei Feng, Ying-Chiao Wang, Chung-Yen Feng
  • Publication number: 20200227264
    Abstract: A semiconductor device includes a gate structure on a substrate, in which the gate structure includes a silicon layer on the substrate, a titanium nitride (TiN) layer on the silicon layer, a titanium (Ti) layer between the TiN layer and the silicon layer, a metal silicide between the Ti layer and the silicon layer, a titanium silicon nitride (TiSiN) layer on the TiN layer, and a conductive layer on the TiSiN layer.
    Type: Application
    Filed: March 27, 2020
    Publication date: July 16, 2020
    Inventors: Tzu-Hao Liu, Yi-Wei Chen, Tsun-Min Cheng, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Po-Chih Wu, Pin-Hong Chen, Chun-Chieh Chiu, Tzu-Chieh Chen, Chih-Chien Liu, Chih-Chieh Tsai, Ji-Min Lin
  • Publication number: 20200227632
    Abstract: Electrically tunable metasurfaces including an array of subwavelength metasurface unit elements are presented. The unit elements include a stacked metal-insulator-metal structure within which an active phase change layer is included. A purely insulator, metal, or coexisting metal-insulator phase of the active layer can be electrically controlled to tune an amplitude and phase response of the metasurfaces. In combination with the subwavelengths dimensions of the unit elements, the phase and amplitude response can be controlled in a range from optical wavelengths to millimeter wavelength of incident light. Electrical control of the unit elements can be provided via resistive heating produced by flow of current though a top metal layer of the unit elements. Alternatively, electrical control of the unit elements can be provided via electrical field effect produced by applying a voltage differential between the top and bottom metal layers of the unit elements.
    Type: Application
    Filed: January 10, 2020
    Publication date: July 16, 2020
    Inventors: Yonghwi Kim, Pin Chieh Wu, Ruzan Sokhoyan, Kelly W. Mauser, Rebecca D. Glaudell, Ghazaleh Kafaie Shirmanesh, Harry A. Atwater
  • Publication number: 20200225386
    Abstract: Compound eyes of insects are great optical system for imaging and sensing by the nature creator, which is an unsurpassed challenge due to its precision and small size. Here, we use meta-lens consisting of GaN nano-antenna to open the fascinating doorway to full-color achromatic light field imaging and sensing. A 60×60 multi-channels meta-lens array is used for effectively capturing multi-dimensional optical information including image and depth. Based on this, the multi-dimensional light field imaging and sensing of a moving object is capable to be experimentally implemented. Our system presents a diffraction-limit resolution of 1.95 micrometer via observing the standard resolution test chart under white light illumination. This is the first mimic optical light field imaging and sensing system of insect compound eye, which has potential applications in micro robotic vision, non-men vehicle sensing, virtual and augmented reality, etc.
    Type: Application
    Filed: December 19, 2019
    Publication date: July 16, 2020
    Inventors: Din-Ping TSAI, Cheng-Hung CHU, Ren-Jie LIN, Mu-Ku CHEN, Pin-Chieh WU
  • Patent number: 10707214
    Abstract: A method of fabricating a cobalt silicide layer includes providing a substrate disposed in a chamber. A deposition process is performed to form a cobalt layer covering the substrate. The deposition process is performed when the temperature of the substrate is between 50° C. and 100° C., and the temperature of the chamber is between 300° C. and 350° C. After the deposition process, an annealing process is performed to transform the cobalt layer into a cobalt silicide layer. The annealing process is performed when the substrate is between 300° C. and 350° C., and the duration of the annealing process is between 50 seconds and 60 seconds.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: July 7, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chia-Chen Wu, Yi-Wei Chen, Chi-Mao Hsu, Kai-Jiun Chang, Chih-Chieh Tsai, Pin-Hong Chen, Tsun-Min Cheng, Yi-An Huang
  • Patent number: 10651040
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a titanium nitride (TiN) layer on a silicon layer; performing a first treatment process by reacting the TiN layer with dichlorosilane (DCS) to form a titanium silicon nitride (TiSiN) layer; forming a conductive layer on the TiSiN layer; and patterning the conductive layer, the metal silicon nitride layer, and the silicon layer to form a gate structure.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: May 12, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Tzu-Hao Liu, Yi-Wei Chen, Tsun-Min Cheng, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Po-Chih Wu, Pin-Hong Chen, Chun-Chieh Chiu, Tzu-Chieh Chen, Chih-Chien Liu, Chih-Chieh Tsai, Ji-Min Lin
  • Publication number: 20190318933
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a titanium nitride (TiN) layer on a silicon layer; performing a first treatment process by reacting the TiN layer with dichlorosilane (DCS) to form a titanium silicon nitride (TiSiN) layer; forming a conductive layer on the TiSiN layer; and patterning the conductive layer, the metal silicon nitride layer, and the silicon layer to form a gate structure.
    Type: Application
    Filed: May 22, 2018
    Publication date: October 17, 2019
    Inventors: Tzu-Hao Liu, Yi-Wei Chen, Tsun-Min Cheng, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Po-Chih Wu, Pin-Hong Chen, Chun-Chieh Chiu, Tzu-Chieh Chen, Chih-Chien Liu, Chih-Chieh Tsai, Ji-Min Lin
  • Publication number: 20190319107
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.
    Type: Application
    Filed: May 22, 2018
    Publication date: October 17, 2019
    Inventors: Chun-Chieh Chiu, Pin-Hong Chen, Yi-Wei Chen, Tsun-Min Cheng, Chih-Chien Liu, Tzu-Chieh Chen, Chih-Chieh Tsai, Kai-Jiun Chang, Yi-An Huang, Chia-Chen Wu, Tzu-Hao Liu
  • Publication number: 20190196068
    Abstract: In this disclosure, an optical component which comprises an array of metalenses is provided. Each metalens comprises a plurality of nanostructures and a dielectric layer and the nanostructures are disposed on the dielectric layer, and the nanostructures comprises an array of first phase compensation structures, and an array of second phase compensation structures. The array of the first phase compensation structures are disposed to surround the array of the second phase compensation structures so as to define a single metalens. The first and second phase compensation structures are complementary to each other and substantially satisfy the Babinet's principle.
    Type: Application
    Filed: December 24, 2018
    Publication date: June 27, 2019
    Inventors: Din-Ping TSAI, Pin-Chieh WU
  • Patent number: 10312242
    Abstract: A semiconductor memory device is provided, and which includes a substrate, plural gates, plural plugs, a capacitor structure and a conducting cap layer. The gates are disposed within the substrate, and the plugs are disposed on the substrate, with each plug electrically connected to two sides of each gate on the substrate. The capacitor structure is disposed on the substrate, and the capacitor structure includes plural capacitors, with each capacitor electrically connected to the plugs respectively. The conducting cap layer covers the top surface and sidewalls of the capacitor structure. Also, the semiconductor memory device further includes an adhesion layer and an insulating layer. The adhesion layer covers the conducting cap layer and the capacitor structure, and the insulating layer covers the adhesion layer.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: June 4, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Tzu-Chieh Chen, Pin-Hong Chen, Chih-Chieh Tsai, Chia-Chen Wu, Yi-An Huang, Kai-Jiun Chang, Tsun-Min Cheng, Yi-Wei Chen
  • Publication number: 20190079321
    Abstract: The optical response of a metasurface is controlled by actuating it via an electrical or magnetic field, temperature control, optical pumping or electromechanical actuation. The metasurface will therefore control the polarization of the incident light. The metasurface comprises an array of patch antennas. The patch antennas are in the form of asymmetrical elements, including rotated rods, cross-shapes, V-shapes, and L-shapes.
    Type: Application
    Filed: September 7, 2018
    Publication date: March 14, 2019
    Inventors: Pin Chieh WU, Ruzan SOKHOYAN, Ghazaleh KAFAIE SHIRMANESH, Harry A. ATWATER
  • Publication number: 20180156949
    Abstract: The present invention provides an optical component comprising a dielectric layer and a nanorod array; the nanorod array is formed on a surface of the dielectric layer and extends along a lateral direction and a vertical direction. The nanorod array comprises a plurality of nanorods extending along the dielectric layer. The nanorods have a gap between one another, and an angle is defined by two adjacent nanorods. A bump is formed at each of two ends of the nanorod.
    Type: Application
    Filed: May 19, 2017
    Publication date: June 7, 2018
    Applicant: Academia Sinica
    Inventors: Din-Ping TSAI, Pin-Chieh WU