Patents by Inventor Ping-Yin Liu

Ping-Yin Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10049901
    Abstract: A method includes placing a first wafer onto a surface of a first wafer chuck, the first wafer chuck including multiple first profile control zones separated by one or more shared flexible membranes. The method also includes setting a first profile of the surface of the first wafer chuck. Setting a first profile of the surface of the first wafer chuck includes adjusting a first volume of a first profile control zone of the multiple first profile control zones. Setting a first profile of the surface of the first wafer chuck also includes adjusting a second volume of a second profile control zone of the multiple first profile control zones, the first volume of the first profile control zone being adjusted independently from the second volume of the second profile control zone, and the second adjustable volume encircling the first adjustable volume.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Ping-Yin Liu, Yen-Chang Chu, Xin-Hua Huang, Lan-Lin Chao, Yeur-Luen Tu, Ru-Liang Lee
  • Publication number: 20180226337
    Abstract: A method of fabricating a semiconductor device includes providing a first substrate comprising a first conductive element exposed at a surface of the first substrate; forming a patterned photoresist layer atop the first conductive element, whereby the patterned photoresist layer provides openings exposing the first conductive element; forming a first metal layer in the openings and directly atop the first conductive element; forming a first insulator layer over the first metal layer and the first substrate; and polishing the first metal layer and the first insulator layer, resulting in a first interface surface over the first substrate wherein the first interface surface includes part of the first metal layer and the first insulator layer.
    Type: Application
    Filed: February 2, 2018
    Publication date: August 9, 2018
    Inventors: Ping-Yin Liu, Kai-Wen Cheng, Xin-Hua Huang, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 10037968
    Abstract: Alignment systems, and wafer bonding alignment systems and methods are disclosed. In some embodiments, an alignment system for a wafer bonding system includes means for monitoring an alignment of a first wafer and a second wafer, and means for adjusting a position of the second wafer. The alignment system includes means for feeding back a relative position of the first wafer and the second wafer to the means for adjusting the position of the second wafer before and during a bonding process for the first wafer and the second wafer.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: July 31, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Xin-Hua Huang, Xiaomeng Chen, Ping-Yin Liu, Lan-Lin Chao
  • Patent number: 10012899
    Abstract: A method includes depositing a first material layer over a first substrate; and depositing a graphene layer over the first material layer. The method further includes depositing an amorphous silicon layer over the graphene layer and bonding the amorphous silicon layer to a second substrate, thereby forming an assembly. The method further includes annealing the assembly, thereby converting the amorphous silicon layer to a silicon oxide layer. The method further includes removing the first substrate from the assembly and removing the first material layer from the assembly, thereby exposing the graphene layer.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: July 3, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chiang Tu, Chun-Lang Chen, Chue San Yoo, Jong-Yuh Chang, Chia-Shiung Tsai, Ping-Yin Liu, Hsin-Chang Lee, Chih-Cheng Lin, Yun-Yue Lin
  • Patent number: 9960129
    Abstract: A method of forming a hybrid bonding structure includes depositing an etch stop layer over surface of a substrate, wherein the substrate comprises a conductive structure, and the etch stop layer contacts the conductive structure. The method further includes depositing a dielectric material over the etch stop layer. The method further includes depositing a first diffusion barrier layer over the dielectric material. The method further includes forming an opening extending through the etch stop layer, the dielectric material and the diffusion barrier layer. The method further includes lining the opening with a second diffusion barrier layer. The method further includes depositing a conductive pad on the second diffusion barrier layer in the opening, wherein a surface of the first diffusion barrier layer is aligned with a surface of the conductive pad.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: May 1, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping-Yin Liu, Szu-Ying Chen, Chen-Jong Wang, Chih-Hui Huang, Xin-Hua Huang, Lan-Lin Chao, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 9957156
    Abstract: An embodiment method includes forming a first plurality of bond pads on a device substrate, depositing a spacer layer over and extending along sidewalls of the first plurality of bond pads, and etching the spacer layer to remove lateral portions of the spacer layer and form spacers on sidewalls of the first plurality of bond pads. The method further includes bonding a cap substrate including a second plurality of bond pads to the device substrate by bonding the first plurality of bond pads to the second plurality of bond pads.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: May 1, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Ming Chen, Ping-Yin Liu, Chung-Yi Yu, Yeur-Luen Tu
  • Patent number: 9953847
    Abstract: A semiconductor structure includes a molding compound, a conductive plug, and a cover. The conductive plug is in the molding compound. The cover is over a top meeting joint between the conductive plug and the molding compound. The semiconductor structure further has a dielectric. The dielectric is on the cover and the molding compound.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: April 24, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ping-Yin Liu, Xin-Hua Huang, Lan-Lin Chao
  • Patent number: 9917069
    Abstract: A method of cleaning an apparatus for processing a semiconductor wafer includes providing a first device having a first surface configured to load a first semiconductor wafer, a second device having a second surface configured to load a second semiconductor wafer, and a first cleaning module; and cleaning the second surface by moving the first cleaning module across the second surface in a first direction with respect to the second device.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: March 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ping-Yin Liu, Yeong-Jyh Lin, Xin-Hua Huang, Chia-Shiung Tsai
  • Publication number: 20180059534
    Abstract: A method includes depositing a first material layer over a first substrate; and depositing a graphene layer over the first material layer. The method further includes depositing an amorphous silicon layer over the graphene layer and bonding the amorphous silicon layer to a second substrate, thereby forming an assembly. The method further includes annealing the assembly, thereby converting the amorphous silicon layer to a silicon oxide layer. The method further includes removing the first substrate from the assembly and removing the first material layer from the assembly, thereby exposing the graphene layer.
    Type: Application
    Filed: November 18, 2016
    Publication date: March 1, 2018
    Inventors: Chih-Chiang Tu, Chun-Lang Chen, Chue San Yoo, Jong-Yuh Chang, Chia-Shiung Tsai, Ping-Yin Liu, Hsin-Chang Lee, Chih-Cheng Lin, Yun-Yue Lin
  • Patent number: 9887155
    Abstract: A semiconductor device including a conductive element and an interface surface fabricated atop the conductive element, and a method for fabricating such a device are described. An exemplary device includes a substrate having a conductive element and a metal layer fabricated atop the conductive element. An oxide layer is fabricated atop the metal layer, thus forming an interface surface. During polishing (e.g., planarization), in which an upper portion of the interface surface is removed, the presence of the interface surface greatly reduces the loading on the conductive element. A second substrate fabricated using the same process may be stacked atop the first substrate and bonded using a hybrid bonding process.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: February 6, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ping-Yin Liu, Kai-Wen Cheng, Xin-Hua Huang, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Publication number: 20170358551
    Abstract: Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together.
    Type: Application
    Filed: August 29, 2017
    Publication date: December 14, 2017
    Inventors: Ping-Yin Liu, Shih-Wei Lin, Xin-Hua Huang, Lan-Lin Chao, Chia-Shiung Tsai
  • Patent number: 9842785
    Abstract: Presented herein is a device comprising a common node disposed in a first wafer a test node disposed in a first wafer and having a plurality of test pads exposed at a first surface of the first wafer. The test node also has test node lines connected to the test pads and that are separated by a first spacing and extend to a second surface of the first wafer. A comb is disposed in a second wafer and has a plurality of comb lines having a second spacing different from the first spacing. Each of the comb lines has a first surface exposed at a first side of the second wafer. The comb lines provide an indication of an alignment of the first wafer and second wafer by a number or arrangement of connections made by the plurality of comb lines between the test node lines and the common node.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: December 12, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Lan-Lin Chao
  • Patent number: 9834435
    Abstract: Structures and formation methods of a semiconductor device structure are provided. A semiconductor device structure includes a semiconductor substrate including a cavity and a movable feature in the cavity. The semiconductor device structure also includes a cap substrate bonded to the semiconductor substrate to seal the cavity. There is an interface between the cap substrate and the semiconductor substrate. The semiconductor device structure further includes a sealing feature embedded in the semiconductor substrate and surrounding the cavity. The sealing feature extends across the interface and penetrates through the cap substrate.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: December 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ping-Yin Liu, Xin-Hua Huang, Yeong-Jyh Lin, Jung-Huei Peng
  • Publication number: 20170338150
    Abstract: Methods for forming an integrated device using CMOS processing with wafer bonding. In an embodiment, a method is disclosed that includes defining an integrated circuit function using a front-end substrate having one or more active devices and a back-end substrate having connections formed in metal layers in dielectric material, wherein the back-end substrate is free from active devices; manufacturing the front-end substrate in a first semiconductor process; more or less simultaneously, manufacturing the back-end substrate in a second semiconductor process; physically contacting bonding surfaces of the front-end substrate and the back-end substrate; and performing wafer bonding to form bonds between the front-end and back-end substrates to form an integrated circuit. Additional methods are disclosed.
    Type: Application
    Filed: August 7, 2017
    Publication date: November 23, 2017
    Inventors: Pin-Nan Tseng, Chia-Shiung Tsai, Ping-Yin Liu
  • Publication number: 20170313581
    Abstract: A method of making a micro electromechanical system (MEMS) package includes patterning a substrate to form a MEMS section. The method further includes bonding a carrier to a surface of the substrate. The carrier is free of active devices. The carrier includes a carrier bond pad on a surface of the carrier opposite the MEMS section. The carrier bond pad is electrically connected to the MEMS section. The method further includes bonding a wafer bond pad of an active circuit wafer to the carrier bond pad. The bonding of the wafer bond pad to the carrier bond pad includes re-graining the wafer bond pad to form at least one grain boundary extending from the wafer bond pad to the carrier bond pad.
    Type: Application
    Filed: July 7, 2017
    Publication date: November 2, 2017
    Inventors: Chun-wen CHENG, Hung-Chia TSAI, Lan-Lin CHAO, Yuan-Chih HSIEH, Ping-Yin LIU
  • Publication number: 20170317118
    Abstract: A device includes two BSI image sensor elements and a third element. The third element is bonded in between the two BSI image sensor elements using element level stacking methods. Each of the BSI image sensor elements includes a substrate and a metal stack disposed over a first side of the substrate. The substrate of the BSI image sensor element includes a photodiode region for accumulating an image charge in response to radiation incident upon a second side of the substrate. The third element also includes a substrate and a metal stack disposed over a first side of the substrate. The metal stacks of the two BSI image sensor elements and the third element are electrically coupled.
    Type: Application
    Filed: July 17, 2017
    Publication date: November 2, 2017
    Inventors: Ping-Yin Liu, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen, Pin-Nan Tseng
  • Publication number: 20170297902
    Abstract: A semiconductor structure includes a first substrate including a cavity extended into the first substrate, a device disposed within the cavity, a first dielectric layer disposed over the first substrate and a first conductive structure surrounded by the first dielectric layer, and a second substrate including a second dielectric layer disposed over the second substrate and a second conductive structure surrounded by the second dielectric layer, wherein the first conductive structure is bonded with the second conductive structure and the first dielectric layer is bonded with the second dielectric layer to seal the cavity.
    Type: Application
    Filed: April 15, 2016
    Publication date: October 19, 2017
    Inventors: HUNG-HUA LIN, PING-YIN LIU, KUAN-LIANG LIU, CHIA-SHIUNG TSAI, ALEXANDER KALNITSKY
  • Patent number: 9786628
    Abstract: A package component includes a surface dielectric layer including a planar top surface, a metal pad in the surface dielectric layer and including a second planar top surface level with the planar top surface, and an air trench on a side of the metal pad. The sidewall of the metal pad is exposed to the air trench.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: October 10, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bruce C. S. Chou, Chen-Jong Wang, Ping-Yin Liu, Jung-Kuo Tu, Tsung-Te Chou, Xin-Hua Huang, Hsun-Chung Kuang, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Publication number: 20170275153
    Abstract: An embodiment method includes forming a first plurality of bond pads on a device substrate, depositing a spacer layer over and extending along sidewalls of the first plurality of bond pads, and etching the spacer layer to remove lateral portions of the spacer layer and form spacers on sidewalls of the first plurality of bond pads. The method further includes bonding a cap substrate including a second plurality of bond pads to the device substrate by bonding the first plurality of bond pads to the second plurality of bond pads.
    Type: Application
    Filed: March 24, 2016
    Publication date: September 28, 2017
    Inventors: Chih-Ming Chen, Ping-Yin Liu, Chung-Yi Yu, Yeur-Luen Tu
  • Patent number: 9754813
    Abstract: A bonding chuck is discussed with methods of using the bonding chuck and tools including the bonding chuck. A method includes loading a first wafer on first surface of a first bonding chuck, loading a second wafer on a second bonding chuck, and bonding the first wafer to the second wafer. The first surface is defined at least in part by a first portion of a first spherical surface and a second portion of a second spherical surface. The first spherical surface has a first radius, and the second spherical surface has a second radius. The first radius is less than the second radius.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: September 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hui Huang, Yen-Chang Chu, Kuan-Liang Liu, Ping-Yin Liu, Cheng-Yuan Tsai, Yeur-Luen Tu, Chia-Shiung Tsai, Ru-Liang Lee