Patents by Inventor Pinghai Hao

Pinghai Hao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8134212
    Abstract: An n-type isolation structure is disclosed which includes an n-type BISO layer in combination with a shallow n-well, in an IC. The n-type BISO layer is formed by implanting n-type dopants into a p-type IC substrate in addition to a conventional n-type buried layer (NBL), prior to growth of a p-type epitaxial layer. The n-type dopants in the BISO implanted layer diffuse upward from the p-type substrate to between one-third and two-thirds of the thickness of the p-type epitaxial layer. The shallow n-type well extends from a top surface of the p-type epitaxial layer to the n-type BISO layer, forming a continuous n-type isolation structure from the top surface of the p-type epitaxial layer to the p-type substrate. The width of the n-type BISO layer may be less than the thickness of the epitaxial layer, and may be used alone or with the NBL to isolate components in the IC.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: March 13, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Pinghai Hao, Seetharaman Sridhar, James Robert Todd
  • Patent number: 8110857
    Abstract: A low noise (1/f) junction field effect transistor (JFET) is disclosed, wherein multiple implants push a conduction path of the transistor away from the surface of a layer upon which the transistor is formed. In this manner, current flow in the conduction path is less likely to be disturbed by defects that may exist at the surface of the layer, thereby mitigating (1/f) noise.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: February 7, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Pinghai Hao, Imran Khan, Joe Trogolo
  • Publication number: 20110309440
    Abstract: An integrated circuit containing an extended drain MOS transistor may be formed by forming a drift region implant mask with mask fingers abutting a channel region and extending to the source/channel active area, but not extending to a drain contact active area. Dopants implanted through the exposed fingers form lateral doping striations in the substrate under the mask fingers. An average doping density of the drift region under the gate is at least 25 percent less than an average doping density of the drift region at the drain contact active area. In one embodiment, the dopants diffuse laterally to form a continuous drift region. In another embodiment, substrate material between lateral doping striations remains an opposite conductivity type from the lateral doping striations.
    Type: Application
    Filed: June 15, 2011
    Publication date: December 22, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Pinghai Hao, Sameer Pendharkar, Binghua Hu, Qingfeng Wang
  • Patent number: 7989853
    Abstract: A dual channel JFET which can be integrated in an IC without adding process steps is disclosed. Pinch-off voltage is determined by lateral width of a first, vertical, channel near the source contact. Maximum drain voltage is determined by drain to gate separation and length of a second, horizontal, channel under the gate. Pinch-off voltage and maximum drain potential are dependent on lateral dimensions of the drain and gate wells and may be independently optimized. A method of fabricating the dual channel JFET is also disclosed.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: August 2, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Pinghai Hao, Sameer Pendharkar, Philip L. Hower, Marie Denison
  • Patent number: 7968936
    Abstract: Fashioning a quasi-vertical gated NPN-PNP (QVGNP) electrostatic discharge (ESD) protection device is disclosed. The QVGNP ESD protection device has a well having one conductivity type formed adjacent to a deep well having another conductivity type. The device has a desired holding voltage and a substantially homogenous current flow, and is thus highly robust. The device can be fashioned in a cost effective manner by being formed during a BiCMOS or Smart Power fabrication process.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: June 28, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Marie Denison, Pinghai Hao
  • Patent number: 7939863
    Abstract: Analog ICs frequently include circuits which operate over a wide current range. At low currents, low noise is important, while IC space efficiency is important at high currents. A vertically integrated transistor made of a JFET in parallel with an MOS transistor, sharing source and drain diffused regions, and with independent gate control, is disclosed. N-channel and p-channel versions may be integrated into common analog IC flows with no extra process steps, on either monolithic substrates or SOI wafers. pinchoff voltage in the JFET is controlled by photolithographically defined spacing of the gate well regions, and hence exhibits low variability.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: May 10, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Pinghai Hao, Marie Denison
  • Publication number: 20100264466
    Abstract: The disclosure herein pertains to fashioning a low noise junction field effect transistor (JFET) where transistor gate materials are utilized in forming and electrically isolating active areas of a the JFET. More particularly, active regions are self aligned with patterned gate electrode material and sidewall spacers which facilitate desirably locating the active regions in a semiconductor substrate. This mitigates the need for additional materials in the substrate to isolate the active regions from one another, where such additional materials can introduce noise into the JFET. This also allows a layer of gate dielectric material to remain over the surface of the substrate, where the layer of gate dielectric material provides a substantially uniform interface at the surface of the substrate that facilitates uninhibited current flow between the active regions, and thus promotes desired device operation.
    Type: Application
    Filed: June 29, 2010
    Publication date: October 21, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Xiaoju Wu, Fan-Chi Frank Hou, Pinghai Hao
  • Patent number: 7786507
    Abstract: A 2-terminal (i.e., anode, cathode) symmetrical bi-directional semiconductor electrostatic discharge (ESD) protection device is disclosed. The symmetrical bi-directional semiconductor ESD protection device design comprises a first and second shallow wells symmetrically spaced apart from a central floating well. Respective shallow wells comprise a first and second highly doped contact implant with opposite doping types (e.g., n-type, p-type). One or more field plates, connected to the central floating well, extend laterally outward from above the central well. The device can be used as an ESD protection device at a bi-directional I/O (e.g., in parallel with a symmetrical MOS to be protected). Upon an ESD event at an input node comprising the first and second shallow wells, a coupled npn-pnp bipolar component comprising the center well, the first and second shallow wells, and the first and second contact implants, is triggered, thereby shunting current from the first to the second shallow well.
    Type: Grant
    Filed: January 6, 2009
    Date of Patent: August 31, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Marie Denison, Pinghai Hao
  • Publication number: 20100171149
    Abstract: A 2-terminal (i.e., anode, cathode) symmetrical bidirectional semiconductor electrostatic discharge (ESD) protection device is disclosed. The symmetrical bidirectional semiconductor ESD protection device design comprises a first and second shallow wells symmetrically spaced apart from a central floating well. Respective shallow wells comprise a first and second highly doped contact implant with opposite doping types (e.g., n-type, p-type). One or more field plates, connected to the central floating well, extend laterally outward from above the central well. The device can be used as an ESD protection device at a bidirectional I/O (e.g., in parallel with a symmetrical MOS to be protected). Upon an ESD event at an input node comprising the first and second shallow wells, a coupled npn-pnp bipolar component comprising the center well, the first and second shallow wells, and the first and second contact implants, is triggered, thereby shunting current from the first to the second shallow well.
    Type: Application
    Filed: January 6, 2009
    Publication date: July 8, 2010
    Applicant: Texas Instruments Incorporated
    Inventors: Marie Denison, Pinghai Hao
  • Patent number: 7745274
    Abstract: The disclosure herein pertains to fashioning a low noise junction field effect transistor (JFET) where transistor gate materials are utilized in forming and electrically isolating active areas of a the JFET. More particularly, active regions are self aligned with patterned gate electrode material and sidewall spacers which facilitate desirably locating the active regions in a semiconductor substrate. This mitigates the need for additional materials in the substrate to isolate the active regions from one another, where such additional materials can introduce noise into the JFET. This also allows a layer of gate dielectric material to remain over the surface of the substrate, where the layer of gate dielectric material provides a substantially uniform interface at the surface of the substrate that facilitates uninhibited current flow between the active regions, and thus promotes desired device operation.
    Type: Grant
    Filed: March 8, 2007
    Date of Patent: June 29, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Xiaoju Wu, Fan-Chi Frank Hou, Pinghai Hao
  • Publication number: 20100155789
    Abstract: A low noise (1/f) junction field effect transistor (JFET) is disclosed, wherein multiple implants push a conduction path of the transistor away from the surface of a layer upon which the transistor is formed. In this manner, current flow in the conduction path is less likely to be disturbed by defects that may exist at the surface of the layer, thereby mitigating (1/f) noise.
    Type: Application
    Filed: February 26, 2010
    Publication date: June 24, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Pinghai Hao, Imran Khan, Joe Trogolo
  • Patent number: 7670888
    Abstract: Fashioning a low noise (1/f) junction field effect transistor (JFET) is disclosed, where multiple implants are performed to push a conduction path of the transistor away from the surface of a layer upon which the transistor is formed. In this manner, current flow in the conduction path is less likely to be disturbed by defects that may exist at the surface of the layer, thereby mitigating (1/f) noise.
    Type: Grant
    Filed: April 11, 2007
    Date of Patent: March 2, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Pinghai Hao, Imran Khan, Joe Trogolo
  • Publication number: 20100032769
    Abstract: An n-type isolation structure is disclosed which includes an n-type BISO layer in combination with a shallow n-well, in an IC. The n-type BISO layer is formed by implanting n-type dopants into a p-type IC substrate in addition to a conventional n-type buried layer (NBL), prior to growth of a p-type epitaxial layer. The n-type dopants in the BISO implanted layer diffuse upward from the p-type substrate to between one-third and two-thirds of the thickness of the p-type epitaxial layer. The shallow n-type well extends from a top surface of the p-type epitaxial layer to the n-type BISO layer, forming a continuous n-type isolation structure from the top surface of the p-type epitaxial layer to the p-type substrate. The width of the n-type BISO layer may be less than the thickness of the epitaxial layer, and may be used alone or with the NBL to isolate components in the IC.
    Type: Application
    Filed: August 10, 2009
    Publication date: February 11, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Pinghai Hao, Seetharaman Sridhard, James Robert Todd
  • Publication number: 20100032728
    Abstract: Analog ICs frequently include circuits which operate over a wide current range. At low currents, low noise is important, while IC space efficiency is important at high currents. A vertically integrated transistor made of a JFET in parallel with an MOS transistor, sharing source and drain diffused regions, and with independent gate control, is disclosed. N-channel and p-channel versions may be integrated into common analog IC flows with no extra process steps, on either monolithic substrates or SOI wafers. pinchoff voltage in the JFET is controlled by photolithographically defined spacing of the gate well regions, and hence exhibits low variability.
    Type: Application
    Filed: August 7, 2009
    Publication date: February 11, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Pinghai HAO, Marie DENISON
  • Publication number: 20100032729
    Abstract: A dual channel JFET which can be integrated in an IC without adding process steps is disclosed. Pinch-off voltage is determined by lateral width of a first, vertical, channel near the source contact. Maximum drain voltage is determined by drain to gate separation and length of a second, horizontal, channel under the gate. Pinch-off voltage and maximum drain potential are dependent on lateral dimensions of the drain and gate wells and may be independently optimized. A method of fabricating the dual channel JFET is also disclosed.
    Type: Application
    Filed: August 7, 2009
    Publication date: February 11, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Pinghai HAO, Sameer PENDHARKAR, Philip L. HOWER, Marie DENISON
  • Publication number: 20100032744
    Abstract: A single poly EEPROM cell in which the read transistor is integrated in either the control gate well or the erase gate well. The lateral separation of the control gate well from erase gate well may be reduced to the width of depletion regions encountered during program and erase operations. A method of forming a single poly EEPROM cell where the read transistor is integrated in either the control gate well or the erase gate well.
    Type: Application
    Filed: August 6, 2009
    Publication date: February 11, 2010
    Applicant: Texas Instruments Incorporated
    Inventors: Jozef C. Mitros, Keith Jarreau, Pinghai Hao
  • Patent number: 7598547
    Abstract: We disclose the structure of a JFET device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It has a buried layer that is electrically communicable to a drain terminal. It has a channel region over the buried layer contacting gate regions that connect to a gate terminal. The channel region, of which the length spans the distance between the buried layer and a source region, is connected to a source terminal. The device current flows in the channel substantially perpendicularly to the top surface of the substrate.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: October 6, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Sameer P Pendharker, Pinghai Hao, Xiaoju Wu
  • Publication number: 20090166721
    Abstract: Fashioning a quasi-vertical gated NPN-PNP (QVGNP) electrostatic discharge (ESD) protection device is disclosed. The QVGNP ESD protection device has a well having one conductivity type formed adjacent to a deep well having another conductivity type. The device has a desired holding voltage and a substantially homogenous current flow, and is thus highly robust. The device can be fashioned in a cost effective manner by being formed during a BiCMOS or Smart Power fabrication process.
    Type: Application
    Filed: December 31, 2007
    Publication date: July 2, 2009
    Inventors: Marie Denison, Pinghai Hao
  • Publication number: 20080251818
    Abstract: Fashioning a low noise (1/f) junction field effect transistor (JFET) is disclosed, where multiple implants are performed to push a conduction path of the transistor away from the surface of a layer upon which the transistor is formed. In this manner, current flow in the conduction path is less likely to be disturbed by defects that may exist at the surface of the layer, thereby mitigating (1/f) noise.
    Type: Application
    Filed: April 11, 2007
    Publication date: October 16, 2008
    Inventors: Pinghai Hao, Imran Khan, Joe Trogolo
  • Publication number: 20080217664
    Abstract: The disclosure herein pertains to fashioning a low noise junction field effect transistor (JFET) where transistor gate materials are utilized in forming and electrically isolating active areas of a the JFET. More particularly, active regions are self aligned with patterned gate electrode material and sidewall spacers which facilitate desirably locating the active regions in a semiconductor substrate. This mitigates the need for additional materials in the substrate to isolate the active regions from one another, where such additional materials can introduce noise into the JFET. This also allows a layer of gate dielectric material to remain over the surface of the substrate, where the layer of gate dielectric material provides a substantially uniform interface at the surface of the substrate that facilitates uninhibited current flow between the active regions, and thus promotes desired device operation.
    Type: Application
    Filed: March 8, 2007
    Publication date: September 11, 2008
    Inventors: Xiaoju Wu, Fan-Chi Frank Hou, Pinghai Hao