Patents by Inventor Pinghai Hao

Pinghai Hao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050064671
    Abstract: A transistor can be fabricated to exhibit reduced channel hot carrier effects. According to one aspect of the present invention, a method for fabricating a transistor structure includes implanting a first dopant into a lightly doped drain (LDD) region to form a shallow region therein. The first dopant penetrates the substrate to a depth that is less than the LDD junction depth. A second dopant is implanted into the substrate beyond the LDD junction depth to form a source/drain region. The implantation of the second dopant overpowers a substantial portion of the first dopant to define a floating ring in the LDD region that mitigates channel hot carrier effects.
    Type: Application
    Filed: September 23, 2003
    Publication date: March 24, 2005
    Inventors: Pinghai Hao, Shanjen Pan, Sameer Pendharkar
  • Publication number: 20050064670
    Abstract: Depletion drain-extended MOS transistor devices and fabrication methods for making the same are provided, in which a compensated channel region is provided with p and n type dopants to facilitate depletion operation at Vgs=0, and an adjust region is implanted in the substrate proximate the channel side end of the thick gate dielectric structure for improved breakdown voltage rating. The compensated channel region is formed by overlapping implants for an n-well and a p-well, and the adjust region is formed using a Vt adjust implant with a mask exposing the adjust region.
    Type: Application
    Filed: September 23, 2003
    Publication date: March 24, 2005
    Inventors: Shanjen Pan, James Todd, Sameer Pendharkar, Tsutomu Kubota, Pinghai Hao
  • Patent number: 6861303
    Abstract: Junction field effect transistors (JFETs) can be fabricated with an epitaxial layer that forms a sufficiently thick channel region to enable the JFET for use in high voltage applications (e.g., having a breakdown voltage greater than about 20V). Additionally or alternatively, threshold voltage (VT) implants can be introduced at one or more of the gate, source and drain regions to improve noise performance of the JFET. Additionally, fabrication of such a JFET can be facilitated forming the entire JFET structure concurrently with a CMOS fabrication process and/or with a BiCMOS fabrication process.
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: March 1, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Pinghai Hao, Fan-Chi Hou, Imran Khan
  • Publication number: 20040235246
    Abstract: The leakage current of an OTP-EPROM cell formed using buried channel PMOS technology can be reduced. The reduction in leakage current of the OTP-EPROM can be achieved by blocking implantation of the Vtp implant into a channel region of an n-well that substantially underlies a floating gate structure. The Vtp implant can be blocked by providing a mask overlying the surface of the channel region of the n-well during implantation of the Vtp implant.
    Type: Application
    Filed: May 21, 2003
    Publication date: November 25, 2004
    Inventors: Xiaoju Wu, Jozef Mitros, Pinghai Hao
  • Publication number: 20040222475
    Abstract: Junction field effect transistors (JFETs) can be fabricated with an epitaxial layer that forms a sufficiently thick channel region to enable the JFET for use in high voltage applications (e.g., having a breakdown voltage greater than about 20V). Additionally or alternatively, threshold voltage (VT) implants can be introduced at one or more of the gate, source and drain regions to improve noise performance of the JFET. Additionally, fabrication of such a JFET can be facilitated forming the entire JFET structure concurrently with a CMOS fabrication process and/or with a BiCMOS fabrication process.
    Type: Application
    Filed: May 9, 2003
    Publication date: November 11, 2004
    Inventors: Pinghai Hao, Fan-Chi Hou, Imran Khan
  • Patent number: 6794700
    Abstract: The present invention provides a capacitor 300, a method of manufacture therefor and an integrated circuit including the same. In one embodiment of the invention, the capacitor 300 includes a first conductive plate 320 located over a semiconductor substrate 310, wherein the first conductive plate 320 has a second conductive plate 340 located thereover. The capacitor 300, in the same embodiment, further includes a dielectric layer 330 located between the first conductive plate 320 and the second conductive plate 340, wherein the dielectric layer 330 includes a Group 17 element.
    Type: Grant
    Filed: April 10, 2003
    Date of Patent: September 21, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Eric Beach, Weidong Tian, Pinghai Hao
  • Publication number: 20040178438
    Abstract: The present invention provides a semiconductor device 200, a method of manufacture therefor and an integrated circuit including the same. In one embodiment of the invention, the semiconductor device 200 includes a floating gate 230 located over a semiconductor substrate 210, wherein the floating gate 230 has a metal control gate 250 located thereover. The semiconductor device 200, in the same embodiment, further includes a dielectric layer 240 located between the floating gate 230 and the metal control gate 250, the dielectric layer 240 having a gettering material located therein.
    Type: Application
    Filed: March 12, 2003
    Publication date: September 16, 2004
    Applicant: Texas Instruments Incorporated
    Inventors: Jozef Mitros, Weidong Tian, Pinghai Hao, Victor Ivanov
  • Publication number: 20040173859
    Abstract: Semiconductor devices and manufacturing methods therefor are disclosed, in which a drain-extended MOS transistor comprises a self-aligned floating region proximate one end of the transistor gate and doped with a first type dopant to reduce channel hot carrier degradation, as well as an oppositely doped first source/drain laterally spaced from the first end of the gate structure in a semiconductor body. The device may further comprise a resurf region doped to a lower concentration than the floating region to facilitate improved breakdown voltage performance. A method of fabricating a drain-extended MOS transistor in a semiconductor device is disclosed, comprising providing first dopants to a floating region in a semiconductor body, which is self-aligned with the first end of a gate structure, and providing second dopants to source/drains of the semiconductor body, wherein the first and second dopants are different.
    Type: Application
    Filed: March 3, 2003
    Publication date: September 9, 2004
    Inventors: Pinghai Hao, Shanjen Pan, Sameer Pendharkar